82C836 Datasheet, PDF (99/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Register Descriptions s
DMA Register Descriptions
The following sections describe the registers used during DMA functions.
Current Address Register
Each DMA channel has a 16-bit Current Address register that holds the address used
during transfers. Each channel can be programmed to increment or decrement this
register whenever a transfer is completed. This register can be read or written by the
CPU in consecutive 8-bit bytes. If Auto-Initialization is selected, this register is reloaded
from the Base Address register upon reaching terminal count in the Current Word Count
register. Channel 0 can be prevented from incrementing or decrementing by setting the
Address Hold bit in the Command register.
Current Word Count Register
Each channel has a Current Word Count register that determines the number of transfers
to perform. The actual number of transfers performed is one greater than the value
programmed into the register. The register is decremented after each transfer until it goes
from zero to FFFFH. When this roll-over occurs, the 82C836 generated T/C, suspends
operation on that channel, sets the appropriate Request Mask bit or Auto-Initialize, and
continues.
Base Word Count Register
This register preserves the initial value of the Current Word Count register. It is also a
write-only register loaded by writing to the Current Word Count register. This register is
loaded in the Current Word Count register during Auto-Initialization.
Command Register
This register controls the overall operation of a DMA subsystem. The register can be
read or written by the CPU and is cleared by either a RESET or a Master Clear
command. See Figure 8-2 for the Command register format.
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