82C836 Datasheet, PDF (54/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Interface
DRAM Interface s
A fundamental assumption of cache systems is that the read data remains the same on
successive reads until subsequently rewritten. This will always be true for memory
read operations (unless address remapping is occurring, and particular addresses don’t
necessarily remain mapped to the same physical memory locations). It is also possible to
cache I/O cycles as long as the basic ‘‘data constancy ’’ assumption is satisfied. Typical
cache schemes may differ radically from each other in the exact strategy they use for
deciding when to update the cache and how to organize the stored tags.
The 82C836 provides the following features for external cache support:
• Three configuration bits in ICR41H allow optional enabling of Early READY mode,
Local Bus Access (LBA) mode, and/or Force Bus Convert mode. The Early READY
mode allows an external cache to claim a nonpipelined, CPU-generated, cycle by
asserting -READY during the first T2 state. The 82C836 does not generate a cycle in
this case, and relies on the external cache to provide the read data or accept the write
data. The result is a two T-state cycle (T1-T2).
• LBA mode is essentially the same as Early READY, except the -0WS input is used
instead of -READY as the cache hit signal, and -READY generation is left entirely
to the external cache controller or other external source. This allows cache
implementations in which -READY needs to be delayed. With an external gate or
multiplexer, the -0WS signal can still be used as a normal AT bus -0WS input even
when LBA mode is enabled. The -LBA and AT bus -0WS signals can simply be
ANDed together (i.e., low-true OR) to provide the -LBA/-0WS input to the 82C836.
• To allow cache implementations to cache 16 bits at a time and also cache AT bus
accesses, the Force Bus Convert mode can be used to force all AT bus reads to be 16
bits, including reads from 8-bit memory or I/O resources. Reads from local DRAM
are always 16 bits automatically, regardless of Force Bus Convert mode. To avoid a
performance penalty when using 8-bit AT bus memory resources such as 8-bit video
memory, the Force Bus Convert feature does not apply to AT bus memory resources
residing in the first 1MB of address space.
• External devices, such as a cache controller, may need a CPU Cycle Start signal if
they do not monitor -ADS and -READY directly. To provide such a signal, the -NA
pin function can be changed by the -DACK3 strap option to operate as a Start Cycle
(-STCYC) signal instead of a Next Address (-NA) signal. The signal can still be used
as a 74F543 address latch enable, if desired, in either case.
The following types of CPU generated cycles can be ‘‘claimed’’ by using the Early
READY or LBA mode:
• Local DRAM reads, but not local DRAM writes; local DRAM writes can be claimed
also, if ICR 63H bit 0 is set. One use for this feature is directly reading and writing
cache data RAM in a diagnostic test.
• AT bus memory reads or writes, I/O reads or writes, and interrupt acknowledge.
When using Early READY or LBA modes, the CPU -NA input must be tied high,
causing the CPU to operate in nonpipelined mode only. This is necessary because of
CPU address timing. The 82C836 may need to generate a local DRAM cycle if the
cycle is not claimed by an external controller, and the 82C836 requires valid CPU
address beyond the point at which it could change in a pipelined cycle.
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