82C836 Datasheet, PDF (34/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Operational Power Management
Functional Description
• The refresh interval during stand-by refresh is programmable: 15 µs, 122µs, 244µs,
or 488µs between refreshes (.5, 2, 4, or 8 cycles of the 32.768KHz input frequency).
• The Power Sense input (PS/MFP5) must remain high during power down in order for
stand-by refresh to work. A logic low level on PS while PWRGOOD is low will clear
the stand-by enable bit in ICR 60H. Since PWRGOOD is low, SCATsx will then
become fully reset.
• During power-down stand-by refresh, the following output signals remain active
instead of becoming high impedance:
° ^{-CAS3, -CAS2, -CAS1 (if multiple RAS active mode is enabled). Refer to Section}
5, System Interface, subsection titled Memory Interface for a detailed discussion of
the multiple RAS active mode and 4MB DRAM Configurations.
° ^{-CAS0, -MWE, -RAS0, -RAS1, -RAS2.}
° ^{-RAS3 (if not using a 4MB DRAM configuration). Refer to Section 5, System}
Interface, subsection titled Memory Interface for a detailed discussion of the
multiple RAS active mode and 4MB DRAM Configurations.
° ^{If a 4MB DRAM configuration is used, MA10 is actively driven to a continuous}
logic high level.
° ^{MA0-9 are actively driven to a continuous logic high level.}
° ^{OSC2 remains actively driven to a continuous logic low level; this is always the}
case during power-down even if the Standby Refresh is disabled.
During normal powered-on operation, the 82C836B can optionally generate fast 8-bit
timing or true 16-bit cycles for video I/O and/or video memory accesses in selected
programmable address ranges (see ICR 61H and 62H). This capability is designed to
improve video performance in products that use on-board video subsystems, including
very compact laptop and notebook PC’s with 8-bit video interfaces.
Operational Power Management
Average system power consumption can be reduced by slowing or stopping the processor
clock during idle periods. If a nonstatic CPU is used, the processor clock can be slowed
down. If a static CPU is used, the processor clock can be stopped completely.
In the 82C836, ‘‘sleep’’ mode is provided in which a HALT instruction, executed by the
CPU, triggers the slowing or stopping of PROCCLK. The sleep mode is enabled by bit 7
in internal configuration register 46H, and bits 1 and 0 determine the frequency of
PROCCLK during sleep mode. The sleep frequency is selectable between 0 (PROCCLK
stopped), CXIN/2, CXIN/4 or CXIN/8.
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