82C836 Datasheet, PDF (72/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Real Time Clock and Internal Timer Registers
Programming the Counter Timer Controller s
Latch Counter Command
When a Latch Counter command is issued, the counter’s output latches (COL and COH)
latch the current state of the CE. COL and COH remain latched until read by the CPU, or
the counter is reprogrammed. The output latches then return to a ‘‘transparent’’ condition.
In this condition, the latches are enabled and the contents of the CE may be read directly.
Latch Counter commands may be issued to more than one counter before reading the first
counter to which the command was issued. Also, multiple Latch Counter commands
issued to the same counter without reading the counter cause all but the first command to
be ignored.
Read-Back Command
The Read-Back command allows the user to check the count value, mode, and state of
the OUT signal and Null Count (NC) flag of the selected counter(s).
The format of the Read-Back command is shown in Figure 6-8.
Figure 6-8. Read-Back Command Format
B7 B6 B5 B4 B3 B2 B1 B0
_________________ ________ ________ ___________________________ ________
0
C<2:0> Counter
LS
Latch Selected Counter
LC
Latch Counter
1
bits: B0
B1-B3
0
C<2:0>
Read as zero.
Writing a one in bit 3 causes Counter 3 to latch one or both of the
registers speicified by LC and LS. The same is true for bits 2 and 1,
except that they enable Counters 1 and 0 respectively.
Each counter’s latches remain latched until either the latch is read or
the counter is reprogrammed.
If LS = LC = 0, status is returned on the next read from the counter.
The next one or two reads (depending on whether the counter is
programmed to transfer one or two bytes) from the counter result in
the count being returned.
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PRELIMINARY
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