82C836 Datasheet, PDF (168/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
a major malfunction in memory refresh, then the standby mode is cleared completely
and the system recovers as if standby mode had not been enabled. The timeout
interval is approximately 15 refresh periods at the currently programmed standby
refresh rate (ICR 60H, bits 4 and 5).
• Since refresh requires the use of -RAS, -CAS, MA, and -MWE signals, these signals
remain active during standby refresh instead of being tristated. (The MA lines are
driven to a continuous logic high level. No refresh address is generated; rather,
CAS-before-RAS refresh must be used along with standby refresh.) The ICR bits for
memory configuration and MRA enable are also preserved during power down if
standby mode is enabled. See the section titled Standby Power Management and
Laptop Support for more precise definition of which outputs remain actively driven
during power-down standby mode.
• Since DACK signals become CAS lines during MRA mode, DACK sampling during
XRST (see Figure 11-19) is suspended when powering back up from standby mode.
The previously sampled state of the DACK lines at the time of initial power
application (before standby mode was enabled) is preserved. (The 82C836B has an
internal hardware interlock to prevent standby mode from becoming or remaining
enabled when external RTC is enabled. This interlock is necessary because the
32KHz input is cut off when external RTC is enabled. Without 32KHz, standby mode
cannot function and the system could lock up if standby mode is enabled.)
In a manufactuirng or test environment, it often happens that the system is powered up
initially with no battery connected. To keep the external PS (MFP5) circuit as simple as
possible, the 82C836B automatically ignores the PS input when PWRGOOD is high. As
soon as PWRGOOD goes high, the 82C836B operates as if PS were high even if PS is
actually still low. (The 82C836A lacks this feature and requires PS to be high before
XRST goes low. In addition, the 82C836A will malfunction if PS goes low at any time
while PWRGOOD is high and XRST is low.)
In a normal operating environment, a battery will have been connected before turning on
the main power supply. In that case, PS (MFP5) will already be high before PWRGOOD
goes high, and PS will remain high during subsequent power-down periods. For the
82C836B, the external PS (MFP5) circuit only needs to insure a brief interval (100ns
should be adequate) of low time on PS (MFP5) after Vcc to the 82C836 has reached 3.0V
(see Figure 3-3).
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PRELIMINARY
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