82C836 Datasheet, PDF (9/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C836 CHIPSet Data Sheet
Contents s
List of Tables
82C836 CHIPSet Introduction
Table 1-1. Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Table 1-2. Bus Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Pin Assignments
Table 2-1. Clock Input and Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Table 2-2. Local Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Table 2-3. Numeric Coprocessor Interface Signals . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-4. Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-5. I/O Channel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 2-6. Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Table 2-7. Alphabetical Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Table 2-8. Numerical Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Functional Description
Table 3-1. Pins for Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Clock/Bus Control
Table 4-1. SCATsx Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
System Interface
Table 5-1. Valid Configurations ----Nonencoded or Encoded RAS . . . . . . . . . 5-6
Table 5-2. Valid Configurations ----Encoded RAS Only . . . . . . . . . . . . . . . . . 5-7
Table 5-3.
4MB DRAM configurations ----Nonencoded RAS Only . . . . . . . . 5-7
Table 5-4.
Memory Address Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Table 5-5.
Memory Configuration Address Ranges and Interleaving
Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6.
Memory Configuration Address Ranges and Interleaving
Sequences Encoded RAS Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7.
Memory Configuration Address Ranges and Interleaving
Sequences Nonencoded RAS Only . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 6-1.
Address Map for the Real Time Clock . . . . . . . . . . . . . . . . . . . . . 6-2
Table 6-2. Format for Clock, Calendar, and Alarm Data . . . . . . . . . . . . . . . . 6-3
Table 6-3. Counter Timer Control I/O Addresses . . . . . . . . . . . . . . . . . . . . . . 6-11
Table 6-4.
Gate Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Interrupt Controller
Table 7-1.
Interrupt Levels for System Board . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Table 7-2.
Interrupt Vector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
DMA Controller
Table 8-1.
DMA Request Levels for Each I/O Channel . . . . . . . . . . . . . . . . . 8-2
Address Maps
Table 9-1.
DMA Controller I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Table 9-2.
Interrupt Controller I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Table 9-3.
Internal Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Table 9-4.
Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Table 9-5.
Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Table 9-6.
Miscellaneous I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 xi