82C836 Datasheet, PDF (20/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Pin Assignments
Signal Descriptions s
Table 2-2. Local Bus Interface Signals
Pin
5-18
20-21
23-30
Type
Bidirectional
Bidirectional
Bidirectional
58
Bidirectional
98
Bidirectional
33
Bidirectional
160
Bidirectional
158
Bidirectional
156
Bidirectional
154
Bidirectional
152
Bidirectional
150
Bidirectional
148
Bidirectional
146
Bidirectional
159
Bidirectional
157
Bidirectional
155
Bidirectional
153
Bidirectional
151
Bidirectional
149
Bidirectional
147
Bidirectional
145
Bidirectional
Name
A<0:13>
A<14:15>
A<16:23>
MODA0
MODA20
-BHE
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
Description
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CPU address, bits 0-23. A0 is also known as -BLE.
These signals are driven by the CPU during CPU
generated bus cycles, by the 82C836 during Refresh
and DMA cycles, and by the add-in card Bus Master
(via address buffers) during Master cycles.
Modified A0 is the internally latched state of CPU
address bit A0 during CPU generated bus cycles. The
82C836 toggles this bit during conversion cycles. The
82C836 also controls MODA0 during Refresh and
DMA cycles, and the add-in card Bus Master controls
it (via address buffers) during Master cycles.
Modified A20 is gated A20 from the 82C836’s gate
A20 logic and should be used instead of CPU A20.
MODA20 is an input during Master cycles.
Byte High Enable is an input from the 80386sx during
CPU and Master cycles, and an output during DMA
cycles. -BHE and A0 indicate the type of bus transfer.
-BHE is pulled high internally.
BHE A0 Function
0 0 Word transfer
0 1 Odd byte transfer
1 0 Even byte transfer
1 1 Reserved
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CPU data bus, bits 0 to 15.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 2-3