82C836 Datasheet, PDF (106/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Register Descriptions
DMA Controller
Special Commands
Five special commands are provided to make the task of programming the device easier.
These commands are activated as a result of a specific address and assertion of either an
-IOR or -IOW. Information on the data lines is ignored by the 82C836 whenever an
-IOW activated command is issued. Thus data returned on -IOR activated commands is
invalid. Decriptions of the five special commands follows:
• Clear Byte Pointer Flip-Flop ----This command is normally executed prior to reading or
writing to the address or word count register. This initializes the flop-flop to point to
the low byte of the register and allows the CPU to read or write the register bytes in
correct sequence.
• Set Byte Pointer Flip-Flop ----Setting the Byte Pointer Flip-Flop allows the CPU to
adjust the pointer to the high byte of an address or word count register.
• Master Clear ----This command has the same effect as a hardware RESET. The
Command Register, Status Register, Request Register, Temporary Register, Mode
Register Counter, and Byte Pointer Flip-Flop are cleared and the Request Mask
Register is set. Immediately following Master Clear or RESET, the DMA is in the
Idle Condition.
• Clear Request Mask Register ----This command enables all four DMA channels to
accept requests by clearing the mask bits in the register.
• Clear Mode Register Counter ----In order to allow access to four mode registers while
only using one address, an additional counter is used. After clearing the counter, all
four mode registers may be read by doing successive reads to the Read Mode Register
address. The order in which the register is read is Channel 0 first and Channel 3 last.
8-1 6 Revision 3.0
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