82C836 Datasheet, PDF (41/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Bus Control Arbitration and Basic Timing
Clock/Bus Control
Table 4-1 summarizes the possible types of bus cycles based on bus owner, target
resource type and bus, and operand type. For CPU cycles alone, there are 78 different
cases; DMA and Master cycles account for an additional 46 and 56 cases, respectively.
SCATsx is designed to handle all these possible cases properly (AT-compatible).
Table 4-1. SCATsx Cycle Types
Size
16-bit
16-bit
8-bit
8-bit
CPU Accesses
Target Resource
Type
Possible Buses
Size
Memory
LD, XD, SD
8, 16
Input/Output
Stx‡, LD†, XD, SD
8, 16
Memory
XD, SD
8, 16
Input/Output
Stx, LD†, XD, SD
8, 16
Operand
Direction
Read/Write
Read/Write
Read/Write
Read/Write
Address
Even, Odd
Even, Odd
Even, Odd
Even, Odd
Total Cases
Total Cases
18^†
24^†
12^†
24^†
78
† Coprocessor accesses are 16-bit if coprocessor is present, 8-bit if absent. For 16-bit operand at o dd address, CPU itself performs two 8-bit transfers; so
16-bit operand at odd address is not counted in the Total Cases column. CPU can also perform INTA, HALT, and Shutdown cycles not listed.
‡ Stx denotes a SCATsx internal resource.
DMA Channel
and I/O Size
16-bit
8-bit
8-bit
I/O Bus
SD
XD^†, SD
XD^†, SD
DMA Transfer
Memory Resources
Size
Bus
Direction
16
LD, XD, SD
Read/Write
16
LD, XD, SD
Read/Write
8
XD, SD
Read/Write
Address
Even
Even, Odd
Even, Odd
Total Cases
Total Cases
6
24
16
46
† DMA I/O resource on XD can be FDD only (Channel 2). Memory resource on XD can be EPROM or video RAM
not listed above.
only. SCATsx can also perform Refresh,
Size
16-bit
16-bit
16-bit
16-bit
8-bit
8-bit
Target Resource
Type
Bus
Memory
LD, XD, SD
Memory
LD, XD, SD
Input/Output
Stx, XD, SD
Input/Output
Stx, XD, SD
Memory
XD, SD
Input/Output
Stx, XD, SD
Master Cycles
Size
16
8
16
8
8
8
Operand^†
Direction
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Address
Even
Even, Odd
Even
Even, Odd
Even, Odd
Even, Odd
Total Cases
Total Cases
6
12
6
12
8
12
56
† Master can reside on SD bus only. Local bus masters are also possible using HOLD/HLDA to get contro l, then generating CPU equivalent protocol.
These cases are included in the CPU Accesses section.
4-6 Revision 3.0
PRELIMINARY
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