82C836 Datasheet, PDF (102/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Register Descriptions
DMA Controller
Request Register
This is a four-bit register used to generate software requests. (DMA service can be
requested either externally or under software control). Request register bits can be set or
reset independently by the CPU. The Request Mask has no effect on software generated
requests. All four bits are read in one operation and appear in the lower four bits of the
byte. Bits 4 through 7 are read as ones. All four request bits are cleared to zero by a
RESET.
Figure 8-4. Request Register (Write Operaton)
B7 B6 B5 B4 B3 B2 B1 B0
______________________________________________ ________ _________________
RS<1:0>Request Channel Select
RB Request Bit
X
bits: B0-B1
B2
B3-B7
RS<1:0>
RB
X
Channel Select 0 and 1 determine which channel’s Mode register is
written to. Read back for the Mode register results in bits 0 and 1
both being ones.
• Channel 0 Select
• Channel 1 Select
• Channel 2 Select
• Channel 3 Select
when RS1 = 0 and RS0 = 0
when RS1 = 0 and RS0 = 1
when RS1 = 1 and RS0 = 0
when RS1 = 1 and RS0 = 1
The request bit is set by writing a one to bit 2. RS1-RS0 select
which bit (channel) is to be manipulated.
These bits are ignored.
8-1 2 Revision 3.0
PRELIMINARY
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