82C836 Datasheet, PDF (67/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Update Cycle
Real Time Clock and Internal Timer Registers
and is maintained until the cycle is complete. Once the cycle is complete, the UIP bit is
cleared and the Update Flag (UF) in register C is set. Figure 6-5 illustrates the update
cycle.
Figure 6-5. Update Cycle
CPU access is always allowed to register A through D during update cycles.
Two methods for reading and writing to the Real Time Clock are recommended. Both
of these methods allow the user to avoid contention between the CPU and the Real Time
Clock for access to the time and date information.
The first method is to read register A, determine the state of the UIP bit. If the UIP is
zero, perform the read or write opertation. For this method to work successfully, the
entire read or write operation (including any interrupt service routines which might
occur) must not require more than 244 µs to complete from the beginning of the read
of register A to the completion of the last read or write operation to the clock Calendar
Registers.
The second method of accessing the lower ten registers is to read register C once and
disregard the contents. Continue reading this register until the UF bit is a one. This bit
becomes true immediately after an update is completed. The user then has until the start
of the next update cycle to comlete a read or write operation.
6-8 Revision 3.0
PRELIMINARY
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