82C836 Datasheet, PDF (186/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s AC Characteristics 25MHz
System Characteristics
DMA to AT-Bus, On-Board I/O, and ROM
Tables 12-34 through 12-36 shows the DMA to AT bus, on-board I/O, and ROM
accesses.
Table 12-34. 197DMA to AT-Bus, On-Board I/O, and ROM----Output Responses
Symbol
t190
t191
t192
t194
t195
t197
t198
t199
t200
t201
t202
t203
Parameters
-DACKn or -DACKEN delay from BUSCLK rise
ALE rise from HLDA rise
DMA Address delay from BUSCLK rise.
Note: DMA address refers to A0-23, MODA0, MODA20, and -BHE
Command fall from BUSCLK rise
Command rise from BUSCLK rise
TC rise from BUSCLK rise
TC fall from BUSCLK rise
LOMEGCS delay from A16-23
HOLD delay from PROCCLK rise at start of T-state
DSELA, B delay from OSC2 rise (MRA mode)
DACKA, B, C valid before DACKEN fall
(MRA mode)
DACKA, B, C hold after DACKEN rise (MRA mode)
Min.
Max.
----
46
----
70
----
35
----
40
----
40
----
40
----
35
----
35
5
25
----
35
0
----
0
----
Table 12-35. DMA to AT-Bus, On-Board I/O, and ROM----Formula Specifications
Symbol
te194
te195
Critical Path
Command low time
Command high time
Formula
t194-t195
t195-t194
Max.
10
10
Table 12-36. DMA to AT-Bus, On-Board I/O, and ROM----Input Requirements
Symbol
t210
t212
t213
t214
t215
Parameters
HLDA setup before BUSCLK rise ^†
DREQ setup before BUSCLK rise ^†
DREQ hold after BUSCLK rise ^†
IOCHRDY setup before BUSCLK rise ^†
IOCHRDY hold after BUSCLK rise ^†
Min.
Max.
15
----
15
----
15
----
10
----
5
----
† These parameters are nonrestrictive. The signal may not be recognized until the subsequent clocking
parameters are violated. The parameter specifies only the condition needed to guarantee recognition
a particular clock edge.
period if these
of the signal on
1 2-1 8 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.