82C836 Datasheet, PDF (61/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Real Time Clock Interface ----MC146818 Compatible
Real Time Clock and Internal Timer Registers
Register Access
Table 6-1 shows the address map for the real time clock.
Table 6-1. Address Map for the Real Time Clock
Column
00
01
02
03
04
05
06
07
08
Function
Seconds
Seconds alarm
Minutes
Minutes Alarm
Hours
Hours alarm
Day of the week
Day of the month
Month
Column
09
0A
0B
0C
0D
0E
0F
10-7F
Function
Year
Register A
Register B
Register C
Register C
Register D
User RAM
User RAM
I/O Ports 70H and 71H are used for accessing the 128 locations in the Real Time Clock.
First the index address (0 to 7FH) is output to port 70H, then the data is read or written at
port 71H. The entire port 70H/71H sequence should be completed while interrupts are
inhibited, or during an interrupt service routine before re-enabling interrupts. Otherwise,
an interrupt service routine could potentially intervene between the output to port 70H
and the subsequent I/O to port 71H, overwriting the port 70H value.
Real Time Clock Address Map
Table 6-1 (shown above) identifies the internal register/RAM organization of the Real
Time Clock portion of the 82C836. The 128 addressable locations in the Real Time
Clock are divided into ten bytes that normally contain the time, calendar and alarm data,
four control and status bytes, and 114 general pupose RAM bytes. All 128 bytes are
readable by the CPU. The CPU may also write to all locations except registers C, D, bit
7 of register A, and bit 7 of the seconds byte, which is always zero.
Time Calendar and Alarm Bytes
The CPU can obtain the time and calendar information by reading the appropriate
locations in the Real Time Clock. Initialization of the time, calendar, and alarm
infomration is accomplished by writing to these locations. Information is stored in
these locations in binary-coded decimal (BCD) format.
Before initialization of the internal register can be performed, the SET bit in register B
should be set to a one to prevent Real Time Clock updates from occuring. The CPU
then initializes the first ten locations in BCD format. The SET bit should then be
cleared to allow updates. Once initialized and enabled, the Real Time Clock performs
clock/calendar updates at a 1Hz rate.
6-2 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.