82C836 Datasheet, PDF (69/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Counter Description
Real Time Clock and Internal Timer Registers
programmed for all six modes, but Mode 1 and Mode 5 have limited usefulness due the
the lack of an external hardware trigger signal. Counter 2 can be operated in any of six
modes listed as follows.
• Mode 0----Interrupt on terminal count
• Mode 1----Hardware retriggerable one-shot
• Mode 2----Rate generator
• Mode 3----Square wave generator
• Mode 4----Software triggered strobe
• Mode 5----Hardware re-triggeralbe strobe
All three counters in the CTC are driven from a common clock TMRCLK (1.19MHz)
derived by dividing OSC1 (14.31818MHz) by 12. Counter zero output (OUT0) is
connected to IRQ0 of INTC1 (see Section 7, Interrupt Controller) and may be used as
an interrupt to the system for time keeping and task switching. Counter 1 is programmed
to generate pulses for use by the refresh generator. The third counter (Counter 2) is a full
function Counter/Timer. This channel can be used as an interval timer, a counter, or as a
gated rate/pulse generator (normally used as a speaker tone generator).
Counter Description
Each counter in the CTC contains a Control Register, a Status Register, a 16-bit Counting
Element (CE), a pair of 8-bit Counter Input Latches (CIL and CIH), and a pair of 8-bit
Counter Output Latches (COL and COH). Each counter also has a clock input for
loading and decrementing the CE, a mode defined GATE input for controlling the
counter (only GATE2 is controlled by I/O port 61H, bit 0), and an OUT signal. The
OUT signal’s state and function are controlled by the Counter Mode and condition of
the CE.
The Control Register stores the mode and command information used to control the
counter. The Control Register may be loaded by writing a byte, containing a pointer to
the desired counter, to thE Write Control Word address (043H). The remaining bits in
the byte contain the mode, type of command, and count format information.
The Status Register allows the software to monitor counter condition and read back the
contents of the Control Register.
The Counting Element is a loadable 16-bit synchronous down-counter. The CE is loaded
or decremented on the falling edge of TMRCLK. The CE contains the maximum count
when a zero is loaded; this is equivalent to 65536 in binary operation or 10000 in BCD.
The CE does not stop when it reaches zero. In Modes 2 and 3, the CE is reloaded. In all
other modes it wraps around to FFFFH in binary operation or 9999 in BCD.
The CE is indirectly loaded by writing one or two bytes (optional) to the Counter Input
Latches which are in turn loaded into the CE. This allows the CE to be loaded or
reloaded in one TMRCLK cycle.
The CE is also read, indirectly, by reading the contents of the Counter Output Latches.
COL and COH are transparent latches that can be read while transparent or latched.
6-1 0 Revision 3.0
PRELIMINARY
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