82C836 Datasheet, PDF(65/205 Page) List of Unclassifed Manufacturers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

82C836 Datasheet, PDF (65/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

◁

s Control and Status Registers

Real Time Clock and Internal Timer Registers

UIE The Update-ended Interrupt Enable bit enables the UF (update end

flag) bit in register C to assert interrupt request. This bit is cleared to

a zero by RESET.

AIE The generation of alarm interrupts is enabled by setting this bit to

a one. Once this bit is enabled, the Real Time Clock generates an

alarm whenever a match occurs between the programmed alarm and

clock information. If the ââdonât careââ condition is programmed into

one or more of the alarm registers, this enables the generation of

periodic interrupts at rates of one second or greater. This bit is

cleared to a zero by RESET.

PIE

The Periodic Interrupt Enable bit controls the generation of interrupts

based on the value programmed into bits B3-B0 of register A. This

allows the user to disable this function without affecting the

programmed rate. Writing a one to this bit enables the generation

of periodic interrupts. This bit is cleared to a zero by RESET.

SET Writing a zero to this bit enables the update cycle and allows the

Real Time Clock to function normally. When set to one, the update

cycle is inhibited and any cycle in progress is aborted. The SET bit

is not affected by the RESET input pin.

Figure 6-3. Register C----Address 0CH (Read Only)

B7 B6 B5 B4 B3 B2 B1 B0

________ ________ ________ ________ __________________________________

IRQF

Update-ended Flag

Alarm Flag

Periodic Interrupt Flag

Interrupt Request Flag

bits: B0-B3

Read as zeros.

The Update-ended Flag bit is set after each cycle. When the UIE bit

is a one, the one in UF causes the IRQF bit to be a one asserting

IRQ. UF is cleared by a register read or by a RESET.

A one appears in the AlarmFlag bit whenever a match has occurred

between the time register and alarm register during an update cycle.

This flag is also independent of its enable (AIE) and generates an

interrupt if AIE is true.

The Periodic interrupt Flag is set to one when a transition, selected

by RS3-RS0, occurs in the divider chain. This bit becomes active

independent of the condition of the PIE control bit. The PF bit then

generates an interrupt and sets IRQF if PIE is one.

6-6 Revision 3.0

PRELIMINARY

Chips and Technologies, Inc.

▷