82C836 Datasheet, PDF (51/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DRAM Interface
System Interface
SCATsx Memory Bank Utilization
The following tables summarize the exact address ranges and interleaving sequences
for each supported memory configuration. It is assumed that shadow RAM is enabled,
internal EMS is disabled, and the top of RAM (ICR 4E) is set to the entire on-board
memory.
Table 5-5. Memory Configuration Address Ranges and Interleaving Sequences
Physical Configuration
00 = no on-board DRAM
01 = 2x256KB
02 = 4x256KB (1M/0)
03 = 4x256KB (640/384)
03 = 4x256KB (640/384)
04 = 6x256KB
04 = 6x256KB
05 = 8x256KB
06 = 4x256KB, 2x1MB
06 = 4x256KB, 2x1MB
07 = 4x256KB, 4x1MB
07 = 4x256KB, 4x1MB
08 = 2x256KB, 2x1MB
08 = 2x256KB, 2x1MB
09 = 2x256KB, 4x1MB
09 = 2x256KB, 4x1MB
0A = 2x256KB, 6x1MB
0A = 2x256KB, 6x1MB
0A = 2x256KB, 6x1MB
0B = 2x1MB
0C = 4x1MB
0D = 6x1MB
0D = 6x1MB
0E = 8x1MB
Address Ranges
None
000000-07FFFFH
000000-0FFFFFH
000000-09FFFFH
100000-15FFFFH
000000-0FFFFFH
100000-17FFFFH
000000-1FFFFFH
000000-0FFFFFH
100000-2FFFFFH
000000-0FFFFFH
100000-4FFFFFH
000000-1FFFFFH
200000-27FFFFH
000000-3FFFFFH
400000-47FFFFH
000000-3FFFFFH
400000-5FFFFFH
600000-67FFFFH
000000-1FFFFFH
000000-3FFFFFH
000000-3FFFFFH
400000-5FFFFFH
000000-7FFFFFH
Map Mode
----
256KW/P
256KW/2WI
256KW/2WI
256KW/2WI
256KW/2WI
256KW/P
256KW/4WI
256KW/2WI
1MW/P
256KW/2WI
1MW/2WI
1MW/P
256KW/P
1MW/2WI
256KW/P
1MW/2WI
1MW/P
256KW/P
1MW/P
1MW/2WI
1MW/2WI
1MW/P
1MW/4WI
Banks
----
0
0, 1
0, 1
0, 1
0, 1
2
0-3
0, 1
2
0, 1
2, 3
1
0
1, 2
0
1, 2
3
0
0
0, 1
0, 1
2
0-3
Page Interleave Size
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----
400H
400H
400H
400H
----
400H
400H
----
400H
800H
----
----
800H
----
800H
----
----
----
800H
800H
----
800H
5-1 0 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.