82C836 Datasheet, PDF (81/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Interrupt Controller
End-Of-Interrupt s
End-Of-Interrupt
End-Of-Interrupt (EOI) is defined as the condition causing an ISR bit to be reset.
Determination of which ISR bit is to be reset can be done by a CPU command (specific
EOI) or the Priority Resolver can be instructed to clear the highest priority IST bit
(nonspecific EOI).
Figure 7-3. Initialization Sequence
START
WRITE ICW1
WRITE ICW2
XA0 = 0 XD4 = 1
XA0 = 1
NO
CASCADE
MODE
YES
WRITE ICW3
XA0 = 1
NO
ICW4?
YES
WRITE ICW4
XA0 = 1
END OF INITIALIZATION
CONTROLLER READY
The 82C836 can determine the correct ISR bit to reset when operated in modes that don’t
alter the fully nested structure, since the current highest priority ISR bit is necessarily the
last level acknowledged and serviced. In conditions where the fully nested structure is
not preserved, a specific EOI must be generated at the end of the interrupt service
routine. An ISR bit that is masked, in Special Mask Mode by an IMR bit, is not cleared
by a nonspecific EOI command.
Optionally, the interrupt controller can generate an Automatic End-Of-Interrupt (AEOI)
on the trailing edge of the second INTA cycle.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 7-5