82C836 Datasheet, PDF (113/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Section 10
Configuration Registers
Internal configuration registers (ICRs) are accessed by addressing an index register at
port 22H and immediately writing (or reading) data to (or from) port 23H. The 82C836
contains ICRs at index values 01H, 40H - 4FH, and 60H - 64H. All ICRs are read/write
unless noted. To avoid unpredictable results, all reserved bits must be written as zero
unless otherwise noted. The value read from a reserved bit is not defined and may vary
unpredictably from one read to the next.
Table 10-1. Index 01H----DMA Wait State Control
Bit
Name
Description
7-6
----
Reserved.
5-4
16-bit DMA
Wait-States
These bits control the number of wait-states inserted during 16-bit DMA
transfers, as follows:
00 = One wait-state (default)
01 = Two wait-states
10 = Three wait-states
11 = Four wait-states
3-2
8-bit DMA
Wait-States
These bits control the number of wait-states inserted during 8-bit DMA
transfers, as follows:
00 = One wait-state (default)
01 = Two wait-states
10 = Three wait-states
11 = Four wait-states
1
DMA XMEMR
In the IBM PC/AT, the assertion of -XMEMR is delayed by one DMA clock
Extension
cycle compared to -XIOR. This may not be desirable in some systems.
0 = Enables delayed -XMEMR function (default).
1 = Starts -XMEMR at the same time as -XIOR.
0
DMA
Clock SEL
This bit allows the user to program the DMA clock to operate at either
BUSCLK or BUSCLK/2. The same DMA clock drives both 8-bit and
16-bit operations.
0 = BUSCLK/2 (default)
1 = BUSCLK
If bit 0 is changed during operation, an internal synchronizer controls the actual
switching of the clock to prevent a short clock pulse from causing a DMA malfunction.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 1 0-1