82C836 Datasheet, PDF (148/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
Cache Mode Write Cycles
Figure 11-9 shows local DRAM write timing when early READY and/or LBA mode is
enabled. The diagram shows a page hit write (zero wait states) followed by a page miss
write (three wait states).
A RAS high write (not shown) has the same timing as a page miss write except the ‘‘RAS
Precharge’’ interval, two T-states in duration, is deleted, resulting in a one wait state
cycle. In a RAS high write, the falling edge of RAS occurs at the middle of the first T2
instead of the middle of the third T2.
There is a slight difference in CAS timing between the 82C836B and the 82C836A. CAS
timing for the 82C836A is shown in dashed lines. 82C836B timing improves the write
data hold delay after CAS goes active.
The ability to perform page hit writes in zero wait states provides a significant
performance benefit in cache-based systems. Since all writes go to DRAM (except in
a diagnostic mode), streamlining write cycles to the same zero wait state performance
as cache hit reads should result in a level of performance approaching buffered
write-through or write-back cache architectures. Actual performance depends on the
number of DRAM banks, DRAM page size, and ratio of DRAM page hits to page misses
on RAS high cycles.
Zero wait state write timing is made possible by allowing CAS to extend into the T1 state
of the next cycle. This also relies on the fact that nonpipeline CPU mode must be used
when early READY and LBA modes are enabled in SCATsx.
If ICR 63H bit zero is set to one, an early wait state is inserted after T1 to allow time for
external logic to claim the cycle via Early READY or LBA.
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