82C836 Datasheet, PDF (14/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C836 CHIPSet Introduction
Architectural Overview s
Table 1-1. Address and Data Buses
Pins
D15-D0
MD15-MD0
XD15-XD0
SD15-SD0
A23-A0
SA19-SA0
UA23-UA17
MA10-MA0
Bus Name
CPU Data
Memory Data
X-Bus
AT Bus Data
CPU Addr
AT Bus Addr
Unlatch Addr
Row/Col Addr
Description
A 16-bit bidirectional bus for data transfer to or from the CPU.
Also used during DMA and master cycles for data transfer to or
from DRAM.
A 16-bit bidirectional bus for data transfer to or from local
DRAM. It should be connected to the D-bus though series
resistors to minimize undershoot and overshoot.
A 16-bit bidirectional bus for data transfer to or from on-board
peripherals
The main 16-bit bidirectional bus for transferring data to or from
add-on cards.
A 24-bit bus, driven primarily by the CPU (80386sx). Driven by
the 82C836 during DMA and refresh cycles.
The main 20-bit address bus for addressing I/O and memory
resources on the AT bus.
An unlatch address bus providing the high-order address bits for
memory resources on the AT bus.
A multiplexed address bus driven by the 82C836 for DRAM row
and column addressing.
Typical on-board I/O resources external to the 82C836 include: keyboard controller,
optional numeric coprocessor, and optional Real Time Clock (RTC). The SCATsx
XD-bus, subject to loading limitations, can also support an on-board video controller,
floppy/hard disk controller, communications ports, parallel port, and/or game port
normally residing on the AT bus.
On-board memory resources external to the 82C836 include the local DRAM and BIOS
EPROM.
In general, all memory and I/O resources, whether on-board or on the AT bus, are either
16-bit or 8-bit resources. 16-bit resources support 16-bit data transfer on all 16 bits of the
respective data bus, as well as 8-bit data transfer to or from an odd address on data bits
8-15, or 8-bit data transfer to or from and even address on data bits 0-7. Note that 16-bit
resources, including the CPU itself always use data bits 0-7 for even-addressed byte
transfers and data bits 8-15 for odd-addressed byte transfers.
8-bit resources, in contrast, always use data bits 0-7, regardless of even or odd addresses,
and can transfer only 8 bits at a time. This disparity between 8-bit resources and 16-bit
resources gives rise to two special cases in data transfer.
Byte Swapping----Whenever a 16-bit resource (or the CPU) transfers a data byte to or
from an 8-bit resource at an odd address, the data on bits 8-15 for the 16-bit resource
must be transferred to or from bits 0-7 for the 8-bit resource. The 82C836 performs this
byte swapping as needed during CPU I/O or memory read/write cycles, DMA cycles, and
Master cycles, including DMA or Master cycles in which both the data source and the
data destination reside on the AT bus.
Chips and Technologies, Inc.
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