82C836 Datasheet, PDF (167/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Timing Relationships
CPU Access to AT-Bus s
Vcc typically ramps up very slowly (perhaps 100ms or more) relative to the high speed
of the 82C836 and CPU. At around 2 or 3VDC, logic that wasn’t already functioning on
battery power begins operating, but PWRGOOD from the power supply remains low.
PWRGOOD typically stays low until several hundred microseconds after Vcc reaches
its valid operational value (4.75VDC minimum).
While PWRGOOD is still low: All outputs except the 14.3MHz driver are held in the
high impedance state. In particular, XRST and CPURST are floating and should be
externally pulled up. PROCCLK and BUSCLK also float. The 14.3MHz driver is held
at a continuous low level. It does not float.
The -DACK lines should be pulled up or down depending on the desired strap options.
-NPERR should be pulled up, but will be driven low if a coprocessor is present.
Eventually, PWRGOOD goes high. At this point, PROCCLK and BUSCLK start
running and the 14.3MHz oscillator is allowed to start running. There will typcially be
a significant start-up time for the 14.3MHz oscillator, potentially 1000 microseconds
or longer.
An internal 1.19MHz clock (14.3MHz divided by 12) starts running when the 14.3MHz
clock starts up. The -DACK lines (strap options) are sampled and latched approximately
128 cycles of 1.19MHz after the 14.3MHz oscillator starts running. After an additional
128 cycles of 1.19MHz, -NPERR is sampled and XRST and CPURST go low. The
sampling of -NPERR is automatic coprocessor-present detection.
There is, therefore, an interval of approximately 200 microseconds during which all
clocks are running and both resets are still high. Allowing BUSCLK and 14.3MHz to
run during reset has been found to be necessary for reliably resetting the 8042/8742
keyboard controller and certain add-on cards on the AT bus.
CPURST can occur alone, without XRST (see the section titled CPU Access to AT Bus).
The pulse width of CPURST in such cases is 22 cycles of PROCCLK, and the falling
edge occurs at the middle of a T-state.
There is no mechanism for synchronizing the 82C836 internal phase clock to any
external source; rather, all phase clocks outside the 82C836 must be synchronized to
the 82C836 via CPURST or XRST.
The foregoing operation is changed as follows when standby mode is enabled:
• If Power Sense (MFP5) is low at any time while PWRGOOD is low, standby mode is
cleared and the system reacts to PWRGOOD exactly as described above. When using
standby mode, the 82C836 and PS (MFP5) signal must remain powered up even when
PWRGOOD is low. In normal system operation, a battery will do this. In a test
environment with no battery connected, standby mode can be tested by driving
PWRGOOD low without actually turning power off.
• When PWRGOOD goes low while standby mode is enabled, the 82C836 attempts to
switch to standby refresh (32KHz based). PWRGOOD is internally blocked from
having any further effect until the switch to 32 KHz based standby refresh is
successful. To prevent disruption of memory refresh, at least one additional normal
refresh must occur before the 82C836 switches to standby refresh. There is a 32 KHz
based timeout to prevent a possible system lockup if normal refresh has stopped
running for any reason (such as erroneous programming by the software). If the
timeout elapses before the switch to standby refresh occurs, indicating that there is
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