82C836 Datasheet, PDF (48/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Interface
DRAM Interface s
Table 5-2. Valid Configurations----Encoded RAS Only
ICR 4DH Bits 4-0 ^x
0FH
10H
11H
12H
13H
14H
15H
16H ^
0 and 1
256KW
256KW
256KW
256KW
1MW
1MW
1MW
1MW
2 and 3
1MW
1MW
1MW
1MW
1MW
1MW
1MW
1MW
4
1MW
1MW
1MW
1MW
1MW
1MW
1MW
1MW
Banks
5
0
1MW
1MW
1MW
0
1MW
1MW
1MW
6
0
0
1MW
1MW
0
0
1MW
1MW
7
0
0
0
1MW
0
0
0
1MW
Total Local Memory
7MB
9MB
11MB
13MB
10MB
12MB
14MB
16MB
K = 1024
M = 1048576
W = word (two bytes)
B = byte
ΠIn all configurations, all memory beyond the first 1MB is available for use as extended memory (addr essed linearly starting at 100000H). Extended memory
can be accessed either directly (in 80386sx protected mode) or through expanded memory address trans lation (EMS).
 RAM above FC0000H is accessible only through EMS. Direct accesses to FC0000H-FFFFFFH by the CPU go to ROM.
Table 5-3. 4MB DRAM configurations----Nonencoded RAS Only
ICR 4DH Bits 4-0 ^x
17H
18H ^
19H
0
256KW
1MW (or 0)
4MW
1
256KW
4MW
4MW
Banks
2
3
4MW
0
0
0
0
0
K = 1024
M = 1048576
W = word (two bytes)
B = byte
ΠThe function of the -RAS3 pin automatically changes to MA10 function whenever a 4MB DRAM configurati
 Bank 1 covers address 0-7FFFFFH and Bank 0 begins at 800000H. Consequently, Bank 0 can remain empty
Bank 0 range (800000H-9FFFFFH), and if ICR 4EH is set to 800000H top-of-RAM address.
4-7
Total Local Memory
0
9 MB
0
10 MB (or 8MB)
0
16 MB
on (17H, 18H, 19H) is selected.
if no internal EMS accesses are performed in the
The row address for the DRAMs comes from higher-order bits of the complete physical
address, while the column address comes from bits 1 through 9 for 256K DRAMs, 1
through 10 for 1MB DRAMs, or 1 through 11 for 4MB DRAMs. Thus, the memory
addresses accessible by changing the column address only, without changing the row
address, are contiguous and constitute a physical memory ‘‘page’’. Successive memory
accesses to the same page do not require -RAS to be cycled, since it is already active and
the row address is already valid. This saves considerable time in memory accessing
because only -CAS needs to be cycled. The SCATsx architecture always uses -CAS only
accessing (also known as page mode) whenever possible. DMA, Master cycles, and
refresh leave -RAS inactive even if the preceding and following CPU memory accesses
are in the same page.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 5-7