82C836 Datasheet, PDF (103/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Register Descriptions s
The format for the Request register read operation is shown in Figure 8-5.
Figure 8-5. Request Register Read Format
B7 B6 B5 B4 B3 B2 B1 B0
____________________________________ ____________________________________
RC<3:0> Request Channel
1
bits: B0-B3
B4-B7
RC<3:0>
1
During a Request register read, the state of the request bit associated
with each channel is returned in bits 0 through 3 of the byte. The bit
position corresponds to the channel number.
These bits are read as ones.
Request Mask Register
The Request Mask register is a set of four bits that are used to inhibit external DMA
requests from generating transfers cycles. This register can be programmed in two ways.
Each channel can be independently masked by writing to the Write Single Mask Bit
location. The data format for this operation is shown as follows:
Figure 8-6. Request Mask Register----Write Single Mask Bit
B7 B6 B5 B4 B3 B2 B1 B0
______________________________________________ ________ __________________
MS<1:0> Select Mask
MB
Mask Bit
X
bits: B0-B1 MS<0:1> These two bits select the specific mask bit that is to be set or reset.
• Channel 0 Select
• Channel 1 Select
• Channel 2 Select
• Channel 3 Select
when MS1 = 0 and MS0 = 0
when MS1 = 0 and MS0 = 1
when MS1 = 1 and MS0 = 0
when MS1 = 1 and MS0 = 1
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