82C836 Datasheet, PDF (57/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Numeric Coprocessor Interface
System Interface
Numeric Coprocessor Interface
The 82C836 contains interface logic that supports use of an 80387sx numeric
coprocessor. The logic provides the following features:
• Precisely times the system reset signal (XRST) to properly synchronize the 80387sx
internal phase clock. Due to pin limitations, the 82C836 does not provide a separate
coprocessor reset signal and does not support coprocessor reset via output to port F1H.
An output to F1H is invaraiably followed by an FINIT instruction, which is sufficient
to insure a full reset of the coprocessor. (FINIT alone is not sufficient for an 80287
because of protected mode, but the 80387sx does not differentiate between protected
and real modes.)
• Automatically detects the presence or absence of the 80387sx by sensing the
coprocessor -ERROR signal during system reset (XRST).
• Detects and latches coprocessor error status.
• Generates an interrupt (IRQ13) to the system when an error occurs, and keeps -BUSY
to the CPU active until error processing has begun, as indicated by an I/O write to port
F0H. (As in all AT-compatible architectures, the -ERROR input to the CPU is not
used.)
• Generates -READY to the CPU if desired or, optionally, relies on the 80387sx to
generate -READY. In order for the 80387sx to generate -READY, an external
three-state inteface, such as that shown in Figure 5-4, is needed between 80387sx
-READYO and 80386sx -READY. If the 82C836 is programmed to generate
-READY during coprocessor accesses, the 80387sx -READYO output should be
left open and the external -READYO interface is unnecessary.
• Generates a dummy -BUSY signal to the CPU when no coprocessor is present (for
compatibility with software packages using certain critical coprocessor instructions
to test for coprocessor presence). The dummy -BUSY signal is just a buffered,
inverted version of -REFRESH.
5-1 6 Revision 3.0
PRELIMINARY
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