82C836 Datasheet, PDF (55/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DRAM Interface
System Interface
If either LBA or Early READY mode is enabled (or both), the 82C836 automatically
generates an Early Wait State at the beginning of every local DRAM read cycle not
claimed by an external controller. This allows time for the external controller to signal a
cache hit before the 82C836 starts a DRAM cycle. The added wait state affects the total
cycle time only in the event of a cache read miss. Cache read hits can be zero wait state
if the external cache controller uses Early READY mode. There is no added wait state
for local DRAM write cycles.
To avoid the need for parity bits in the cache SRAMs, parity checking on local DRAM
read cycles is suspended in the event of a cache hit. Parity checking of local DRAM
memory operates normally on cache misses.
When using both local memory caching and internal EMS, the EMS page windows and
EMS target areas (expanded memory) must be excluded from the cacheable address
ranges. Since EMS address translation is entirely internal to the 82C836, a local memory
cache only has access to CPU addresses, not translated EMS addresses.
Expanded/Extended Memory
The 82C836 fully supports the LIM EMS 4.0 and 3.2 specifications. EMS allows
operating systems and software applications to access memory above the 1MB DOS limit
through a page mapping scheme managed by an EMS driver. The SCATsx architecture
allows up to 64KB of address space in the first 1MB to be remapped, in 16KB pages, to
anywhere in the 16MB address space, described as follows:
• Remappable area ----The remappable address range is either 0D0000-0DFFFFH or
0E0000-0EFFFFH, determined by a bit in one of the EMS I/O ports (see below). In
LIM EMS terminology, this 64KB remappable address range is referred to as the Page
Frame.
• Page windows and target pages ----The remappable address range is divided into
four page windows of 16KB each. Each page window can be mapped to any 16KB
target page anywhere in the 16MB address space. In LIM EMS terminology, the
page windows are referred to as physical pages because these have fixed physical
addresses. The target pages are referred to as logical pages because these have
logical addresses only ----until mapped into a physical page within the page frame.
• Page registers ----Associated with each page window is a page register. The 82C836
contains four page registers, one for each 16KB page window. Each page register
specifies the absolute physical location of the 16KB target page to be mapped into
the associated page window. Each page register also specifies whether or not the
associated page window is enabled or disabled, i.e., whether or not to perform EMS
address remapping in that window. If a page window is disabled, accesses to that
window are treated as ordinary non-EMS memory accesses.
• EMS I/O ports ----The page registers are accessed using three I/O ports located at either
I/O addresses 208H-20AH or 218H-21AH (selectable via ICR 4F bit 0). In I/O port
20AH (or 21AH), bits 1-0 specify which page register is currently accessible. The
selected page register is then accessed at I/O ports 208H and 209H (or 218H and
219H).
• EMS enable/disable ----EMS translation can be enabled or disabled by ICR 4F bit 7. In
addition, the EMS I/O ports can be enabled or disabled by ICR 4F bit 6.
5-1 4 Revision 3.0
PRELIMINARY
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