82C836 Datasheet, PDF (139/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Timing Relationships
CPU Access to AT-Bus s
Figure 11-4. -MEMCS16 and -IOCS16 Timing
When an attached memory resouce detects an address in its assigned range, it should
assert -MEMCS16. When an attached I/O resource detects an address in its assigned
range, it should assert -IOCS16. Since there is no way for a device on the AT bus to
know whether the cycle is a memory access or I/O access prior to a command signal
going active, it is possible for -IOCS16 and -MEMCS16 both to be asserted
simultaneously by different AT bus add-on cards.
As previously shown in Figure 11-1, the 82C836 (via -NA) latches address bits 1-23 on
the AT bus before the start of ALE, and keeps the address latched until after the end of
the command pulse. MODA0 also follows the same timing, except for the low to high
transtion after the first cycle of a bus conversion.
The 82C836 requires -MEMCS16 to be valid at the end of ALE i.e., from slightly before
the falling edge of ALE until slightly after ALE falls.
The 82C836 samples -IOCS16 on the first rising edge of BUSCLK after I/O command
goes active (low), -IOCS16 must remain valid until the end of the I/O command.
Although -MEMCS16 and -IOCS16 normally are asserted by 16-bit resources on the AT
bus, the 82C836 can assert either or both of these signals in the following cases:
• During on-board ROM read, if on-board ROM is 16 bits wide.
• During CPU, DMA or Master access to on-board DRAM.
• During access to EMS I/O Ports 2x8H and/or 2x9H (where x is programmable as
either 0 or 1). A byte access to either port, or a word access at I/O address 2x8H,
results in assertion of IOCS16. These two EMS I/O ports operate as a 16-bit I/O
resource; data transfer to or from 2x9H always uses D8-15 and/or XD8-15.
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