82C836 Datasheet, PDF (130/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Configuration Registers
82C386 CHIPSet Data Sheet
Port 61H controls several system-level functions. The port can be accessed through any
odd I/O port address from 61H through 6FH.
Table 10-23. Port 61H----Control Port/Status
Bit
Name
Description
7
Parity Error
(read only)
This bit (if 1) indicates that a parity error has been detected during a local
memory read. Causes NMI if Port 70H bit 7 is 0.
6
IOCHCK
(read only)
This bit (if 1) indicates an I/O channel check has occured (usually a parity
error) on the system I/O channel. Causes NMI if port 70H bit 7 is 0.
5
TMR 2 Out
(read only)
This bit returns the condition of the timer 2 output (speaker tone).
4
Refresh Detect
This bit toggles on each refresh cycle.
(read only)
3
CHCK DIS
(read/write)
This bit clears and disables the internal I/O Channel Check detection latch.
1 = Latch clear and disable. Bit 6 still responds to IOCHCK
(unlatched) but does not cause NMI.
0 = Enable I/O Channel Check detection.
2
Parity Disable
This bit, if set, clears and disables the internal parity error detection latch.
(read/write)
1 = Parity error latch clear and disable.
0 = Parity checking enable (default), if ICR 46H bit 6 is also zero.
1
SPKR Data
(read/write)
This bit gates the output of channel 2 of the timer/counter (speaker tone).
1 = Output is enabled, i.e., speaker tone on.
0 = Output is forced low (default)
0
TMR 2 Gate
This bit gates the clock input for timer channel 2 (speaker tone).
(read/write)
1 = Channel 2 timer clock enabled.
0 = Channel 2 timer clock disabled (default).
1 0-1 8 Revision 3.0
PRELIMINARY
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