82C836 Datasheet, PDF (204/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Appendix A
Differences Between
82C836A and 82C836B
The 82C836B corrects various anomalies found in the 82C836A. Refer to Product Alert
204.2/2-92 for details regarding these anomalies. The additional differences between
82C836A and 82C836B are as follows:
For the 82C836A:
• ICRs 61H and 62H are reserved. Fast video mode is not supported.
• ICR 46H bit 5 is reserved. There is no option to remap high ROM addresses above
15MB to shadow RAM below 1MB.
• ICR 64H bit 7 is reserved. The 82C836A always ignores any CPU cycles that begin
during CPU reset.
• The 82C836A does not support hidden refresh.
• During DRAM write operations in early READY mode, the 82C836A delays CAS
assertion by one half-cycle of PROCCLK compared to the 82C836B. Although this
allows extra margin for write data and parity setup before CAS falls, it also reduces
the worst-case timing margin for write data hold after CAS falls. The 82C836B
greatly reduces the parity generation delay as well as improving CAS timing to allow
an increased worst-case margin for DRAM write data hold time.
• Several differences in AC timing parameters are noted in Section 12, System
Characteristics.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 A-1