82C836 Datasheet, PDF (177/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Characteristics
AC Characteristics 16- and 20MHz s
Table 12-14. DMA to AT-Bus, On-board I/O, and ROM----Input Requirements
Symbol
t210
t212
t213
t214
t215
Parameters
HLDA setup before BUSCLK rise ^†
DREQ setup before BUSCLK rise ^†
DREQ hold after BUSCLK rise ^†
IOCHRDY setup before BUSCLK rise ^†
IOCHRDY hold after BUSCLK rise ^†
16MHz
Min. Max.
20 ----
20 ----
20 ----
15 ----
7
----
20MHz
Min. Max.
15 ----
15 ----
15 ----
10 ----
5
----
† Certain input parameters, as noted, are nonrestrictive. The signal may not be recognized until the subsequent clocking
period if these parameters are violated. The parameter specifies only the condition needed to guara ntee recognition of the
signal on a particular clock edge.
DMA and AT-Bus Master Access to Local Memory
Tables 12-15 through 12-17 are the specification requirements for the DMA and the AT
bus master to access local memory. Note: For XD, D, and PAR timing, use t145-t148
and t112. For row/column change over and CAS active, use t102, t105, and t107.
Table 12-15. DMA and AT-Bus Master Access to Local Memory----Output Responses
Symbol
t230
t231
t232
t233
t234
t235
t236
t239
t240
t241
t242
Parameters
-RAS high from HLDA rise
A0-23 and -BHE float from -MASTER active
Command float from -MASTER active
-MWE rise from -XMEMR fall
-MWE fall from -CAS rise
-RAS inactive from -XMEMR or -XMEMW high
-CAS inactive from -XMEMR or -XMEMW high
-RAS active from XMEMR or XMEMW
A20 valid from MODA20 during MASTER access
A0 valid from MODA0 during MASTER access
SDIRL, H fall from -XMEMW fall during Master
write
16MHz
Min. Max.
---- 60
---- 60
---- 35
---- 45
2
60
---- 45
---- 55
---- 36
---- 25
---- 24
---- 40
20MHz
Min. Max.
---- 60
---- 60
---- 30
---- 40
2
60
---- 42
---- 50
---- 36
---- 25
---- 24
---- 40
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