82C836 Datasheet, PDF (142/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
-CAS Only DRAM Access by CPU
Figure 11-6 shows the fastest possible CPU accesses to local DRAM. -RAS and row
address are already valid from a previous cycle, so only -CAS needs to be cycled. The
basic protocol is:
• Column address becomes valid at start of TS.
• -CAS goes low one PROCCLK later (for read), four PROCCLKs for write.
• -CAS stays low until end of cycle.
• Read data becomes valid by end of cycle.
• Write data and parity are valid at mid-TS.
In pipeline mode, the shortest possible local memory read cycle is two T-states: T1P,
T2P. The shortest possible pipelined memory write is T1P, T2P, T2P (three T-states).
The extra T2P during writes allows time for parity generation. Nonpipelined cycles
follow the same timing except for an added T1 state at the beginning.
The -CAS active time is three PROCCLK cycles for read, and two PROCCLK cycles for
write. The minimum -CAS high (precharge) time is one cycle of PROCCLK. Minimum
column address setup time before -CAS goes active is one PROCCLK. Minimum
column address hold time after -CAS goes active is also one PROCCLK.
For external cache support, the end of the -CAS pulse has a small additional propagation
delay built-in so the read data will remain valid long enough for the cache data RAM to
capture it (cache read miss cycle). See the section titled Early READY and LBA Modes
for other cache related timing.
-MWE is normally low so it can be used externally as a memory data buffer direction
control if desired. A small extra -MWE delay is provided at the end of the -CAS pulse
to insure that -CAS always goes inactive before -MWE goes back low. If the cycle is
nonpipelined, the falling edge of -MWE is delayed until the middle of the next T-state.
If the ‘‘-CAS Extend ’’ wait state is enabled, one additional T-state is inserted in the -CAS
active time.
If internal EMS, Early READY mode or LBA is enabled (individually or in any
combination), an extra T-state may be inserted at the beginning of the cycle before
-CAS goes active. The extra T-state allows time for EMS address translation and/or
cycle claiming by external logic such as a cache controller. In the case of Early READY
or LBA, the early wait state occurs only on bus cycles that can be claimed by external
logic, and only if the cycle is not externally claimed. In the case of internal EMS, the
early wait state occurs only if access is made to one of the four page windows and the
window has been enabled for EMS, i.e., only if an EMS address translation actually
needs to occur.
ALE and command are not generated on the AT bus during local memory accesses by
the CPU.
The CPU status signals (M/-IO, D/-C, W/-R) are latched internally at mid-TS.
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PRELIMINARY
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