82C836 Datasheet, PDF (94/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Operations
DMA Controller
Program Condition
The Program condition is entered whenever HLDA is inactive and internal select is
active. The internal select is derived from the top-level decode (described earlier).
During this time, address lines A0-A3 become inputs if DMA1 is selected, or A1-A4
become inputs if DMA2 is selected.
Note: When DMA2 is selected, A0 is ignored.
These address inputs are used to select the DMA controller registers to be read or written.
Due to the large number of internal registers in the DMA subsystem, an internal flip-flop
is used to supplement the addressing of the count and address registers. This bit is used
to select between the high and low bytes of these registers. The flip-flop toggles each
time a read or write occurs to any of the word count or address registers in the DMA.
The internal flip-flop is cleared by a hardware RESET or a Master Clear command and
may be set or cleared by the CPU issuing the appropriate command.
Special commands are supported by the DMA subsystem in the Program condition to
control the device. These commands do not make use of the data bus, but are derived
from a set of addresses, the internal select, and -IOW or -IOR. These commands are
Master Clear, Clear Register, Clear Mode Register Counter, Set, and Clear Byte Pointer
Flip-Flop.
The 82C836 enables programming whenever HLDA has been inactive for one DMA
clock cycle. It is the responsibility of the system to ensure that programming and HLDA
are mutually exclusive. Erratic operation of the 82C836 can occur if a request for service
occurs on an unmasked channel that is being programmed. The channel should be
masked, or the DMA disabled, to prevent the 82C836 from attempting to service a device
with a channel which is partially programmed.
Active Condition
The 82C836 DMA subsystem enters the Active condition whenever a software request
occurs or a DMA request on an unmasked channel occurs, and the device is not in the
Program condition. The 82C836 then begins a DMA transfer cycle.
In an I/O-to-memory cycle, for example, after receiving a DREQ, the 82C836 asserts
HOLD to the CPU. On the next clock cycle, the DMA exits the Idle condition and enters
state S0, where it remains until HLDA is returned. After detecting HLDA, the DMA
enters state S1, during which the DMA controller generates the memory address, resolves
priority and issues DACK on the highest priority channel requesting service. The DMA
then proceeds to state S2, at which time the 82C836 asserts -XIOR. Next, the device
transitions into S3, where the -XMEMW command is asserted. This is followed by a
minimum of one DMA wait state, SW, where the 82C836 remains until the wait-state
counter has decremented to zero and IOCHRDY is true. At least one SW always occurs,
but the S3 state can be deleted if the compressed timing is selected. Once a ready
condition is detected, the DMA enters S4, where both commands are deasserted. In
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