82C836 Datasheet, PDF (38/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Clock/Bus Control
Bus Control Arbitration and Basic Timing s
After PWRGOOD goes high, indicating that all voltages are within specification, the
82C836 generates reset pulses on XRST and CPURST to reset the system and CPU.
While XRST is active, the DACK lines are sampled and latched for the strap options.
The 82C836 also samples and latches -NPERR from the coprocessor to determine
whether or not a coprocessor is present.
The timing of the falling edges of XRST and CPURST is critical for proper clock
synchronization. System timing generated by the CPU consists of T-states, each of
which consists of two cycles of PROCCLK. The 80386sx and 80387sx contain internal
‘‘phase’’ clocks that track the first and second PROCCLK cycle of each T-state. For
proper system operation, it is essential to synchronize both of these phase clocks and a
similar phase clock inside the 82C836. An external cache controller, if implemented,
also needs a phase clock if it relies on -ADS and -READY for cycle tracking.
The master phase clock for the entire system is the 82C836 phase clock, which is a free
running divide-by-two from PROCCLK. The 82C836, in turn, precisely controls the
timing of XRST and CPURST to synchronize all other phase clocks throughout the
system. There is no provision for synchronizing the 82C836 master phase clock to an
external source; rather, all external phase clocks must be synchronized to the 82C836 by
means of XRST or CPURST. See Section 11, System Timing Relationships for additional
timing information.
Bus Control Arbitration and Basic Timing
The 82C836 supports an IBM PC AT-compatible I/O channel, also known as the AT
bus. An internal bus controller, which is functionally similar to an 82288 bus controller,
provides command generation and timing control for the AT-compatible I/O channel.
This allows the processor to run faster than the I/O channel, DMA commands, and
timing. Accesses to the I/O channel can be programmed to run slower than the local
bus cycles.
Although the local bus is normally controlled by the CPU, the 82C836’s internal DMA
controller or refresh controller can request control by issuing a HOLD request to the
CPU. When this occurs, the 80386sx relinquishes control and issues HLDA (hold
acknowledge) to the 82C836.
The conditions capable of triggering HOLD are as follows:
• System initiated refresh ----82C836 issues HOLD without any external prompting,
based on the AT-compatible refresh timer.
• DMA request ----82C836 issues HOLD in response to a DREQ input. Upon receiving
HLDA, the 82C836 asserts the appropriate DACK signal. Next, depending on
whether or not the DMA Channel has been programmed for ‘‘cascade’’ mode, the
82C836 generates one or more DMA cycles or waits for -MASTER to be asserted by
an add-in card bus master. (See Section 8, DMA Controller, subsection titled DMA
Controller----8237 Compatible),
• Master request ----82C836 follows the same DREQ/DACK protocol as for DMA, then
waits for the add-on Master to perform Master cycles as needed and eventually release
DREQ. If the Master initiates a refresh (by driving -REFRESH low), the 82C836
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