82C836 Datasheet, PDF (95/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Operations s
Burst mode and Demand mode, subsequent cycles begin in S2, unless the intermediate
address bits require updating. In these subsequent cycles, the lower address bits are
changed in S2. The DMA can be programmed on a channel-by-channel basis to operate
in one of four modes. The four mode are described as follows:
• Single Transfer Mode ----This mode directs the DMA to execute only one transfer cycle
at a time. DREQ must be held active until DACK becomes active. If DREQ is held
active throughout the cycle, the 82C836 deasserts HRQ and releases the bus after the
transfer is complete. After HLDA is inactive, the 82C836 again asserts HRQ and
executes another cycle in the same cycle; unless a request from a higher priority
channel is received. In this mode, the CPU is allowed to execute at least one bus cycle
between transfers. Following each transfer, the word count is decremented and the
address is incremented or decremented. When the word count decrements from
0000H to FFFFH, the terminal count bit in the status register is set and a T/C pulse is
generated. If auto-initialization option is enabled, the channel reinitialized itself. If
auto-initialize is not selected, the DMA sets the DMA request bit mask and suspends
transferring on the channel.
• Block Transfer Mode ----When Block Transfer Mode is selected, the 82C836 begins
transfers in response to either a DREQ or a software request. This continues until a
terminal count (FFFFH) is reached, at which time TC is pulsed and the status register
terminal count bit is set. In this mode DREQ need only be held active until DACK is
asserted. Auto-initialization is operational in this mode also.
• Demand Tranfer Mode ----In Demand Transfer Mode, the DMA begins transfers in
response to the assertion of DREQ and continues until either terminal count is reached
or DREQ becomes inactive. This mode is normally used for peripherals with limited
buffering availability. The perpheral can initiate a transfer and continue until its
buffer capacity is exhausted. The peripheral may re-establish service by again
asserting DREQ. During idle periods, between transfers, the CPU is released to
operate and can monitor the operation by reading intermediate values from the address
and word count register. Once DREQ is deasserted, higher priority channels are
allowed to intervene. Reaching terminal count results in the generation of a TC pulse,
the setting of the terminal count bit in the status register, and auto-initialization (if
enabled).
• Cascade Mode ----This mode is used to interconnect more than one DMA controller, to
extend the number of DMA channels while preserving the priority chain. In Cascade
mode, the master DMA controller does not generate address or control signals. The
DREQ and DACK signals of the master are used to interface the HRQ and HLDA
signals of the slave DMA devices. Once the master has received an HLDA from the
CPU in response to a DREQ caused by the HRQ from a slave DMA controller, the
master DMA controller ignores all inputs except HLDA from the CPU and DREQ on
the active channel. This prevents conflicts between the DMA devices.
Figure 8-1 (shown earlier), portrays the cascade interconnection between the two levels
of DMA devices. Note, Channel 0 of DMA2 is internally connected for Cascade mode to
DMA1. Additional devices can be cascaded to the available channels in either DMA1 or
DMA2 since cascade is not limited to two levels for DMA controllers.
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Revision 3.0 8-5