82C836 Datasheet, PDF (66/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Real Time Clock and Internal Timer Registers
Update Cycle s
B7
IRQF The Interrupt Request Flag is set to one when any of the conditions
that can cause an interrupt is true and the interrupt enable for that
condition is true. The condition that causes this bit to be set also
generates an interrupt. The logical expression for this flag is:
IRQF = PF & PIE + AF & AIE + UF & UIE
This bit and all other active bits in this register are cleared by reading
this register or by activation the -PS input pin. Writing to this
register has no effect on the contents.
Figure 6-4. Register D----Address 0DH (Read Only)
B7 B6 B5 B4 B3 B2 B1 B0
________ ________________________________________________________________
0
VRT
Valid RAM and Time
bits: B0-B6 0
B7
VRT
Read as zeros.
The Valid RAM and Time bit indicates the condition of the contents
of the Real Time Clock. This bit is cleared to a zero whenever the
PS input pin is low. This pin is normally derived from the power
supply, which supplies Vcc to the device and allows the user to
determine whether the registers have been intialized since power was
applied to the device. PWRGOOD has no effect on this bit, and it
can only be set by reading register D. All unused register bits will be
zero when read and are not writeable.
Update Cycle
During normal operation, the Real Time Clock performs an update cycle once every
second. The performance of an update cycle is contigent upon the divider bits DV<0:2>
not being cleared. The function of the update cycle is to increment the clock/calendar
registers and compare them to the Alarm Registers. If a match occurs between the two
sets of register, an alarm is issued. An interrupt is issued if the alarm and interrupt
control bits are enabled.
While an update is taking place, the lower ten registers are unavailable to the CPU.
This is done to prevent the possible corruption of data in the register or the reading of
incorrect data. To avoid contention problems between the Real Time Clock and the
CPU, a flag is provided in register A to alert the user of an impending update cycle.
This Update In Process (UIP) bit is asserted 244 µs before the actual start of the cycle
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Revision 3.0 6-7