82C836 Datasheet, PDF (140/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
IOCHRDY and OWS
Figure 11-5 shows the effect of IOCHRDY and -0WS during CPU accesses to the AT
bus. If IOCHRDY and -0WS both remain high, the command width is determined by the
defaults listed earlier. The default command timing is represented by the dashed lines.
IOCHRDY can increase the command width, while 0WS can reduce it.
Figure 11-5. IOCHRDY and -0WS
IOCHRDY is first checked at time A, one BUSCLK before the default end of command
(B). Detection of IOCHRDY low at time A causes the command to remain active for
an additional BUSCLK. IOCHRDY is sampled again on each successive rising edge
of BUSCLK until it is detected high. The command ends exactly one BUSCLK after
IOCHRDY is detected high.
-0WS is checked on each falling edge of BUSCLK after command is active. Detection of
-0WS low causes the command to end of the next rising edge of BUSCLK. -0WS is
operative in this manner on all CPU accesses to the AT bus, including I/O as well as
memory, 8-bit as well as 16-bit.
It is not valid for IOCHRDY and -0WS both to be low during the same bus cycle.
Neither IOCHRDY nor -0WS is ever driven by the 82C836. These signals are 82C836
inputs only.
1 1 -8 Revision 3.0
PRELIMINARY
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