82C836 Datasheet, PDF (183/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Characteristics
AC Characteristics 25MHz s
CPU to Local Memory
Tables 12-28 through12-30 provides the timing requirements for the CPU to access
local memory.
Table 12-28. CPU to Local Memory----Output Responses
Symbol
t100
t101
t102
t103
t104
t105
t106
t107
t108
t109
t110
t111
t112
t113
Parameters
RAS active from PROCCLK rise
RAS inactive from PROCCLK rise
CAS active from PROCCLK rise
CAS inactive from PROCCLK rise
Row address valid from PROCCLK rise
Row address hold from PROCCLK rise
Row address valid from A0-23 in
Column address valid from PROCCLK rise
Column address hold from PROCCLK rise
Column address valid from A0-23 in
-MWE fall from -CAS rise
-MWE rise from PROCCLK rise (C _L = 30pF)
PARL, PARH valid from D0-15 write data in
-READY delay from PROCCLK rise
* 30ns maximum for 82C836A.
** 58ns maximum for 82C836A.
Min.
Max.
----
23
----
26
----
23
----
27
----
32*
0
----
----
50
----
19
0
----
----
47
0
36**
----
26
----
55
4
31
Table 12-29. CPU to Local Memory----Formula Specifications
Symbol
te101
te102
te103
te103a
te104
te105
te106
te107
te108
te109
te111
te112
Critical Path
RAS precharge
RAS to CAS delay
CAS precharge
CAS rise to RAS fall
Row address setup before RAS
Row address hold after RAS
Row address setup before RAS
Column address setup before CAS
Column address hold after CAS
Column address setup before CAS
MWE rise before CAS fall
Write parity setup before CAS
* 13ns maximum for 82C836A.
** 5ns maximum for 82C836A.
Formula
t101-t100
t100-t102
t103-t102
t103-t100
t104-t100
t100-t105
t106-t100
t107-t102
t102-t108
t109-t102
t111-t102
t112-t102
Max.
19**
9
7
6
11
5
28
6
2
25
6*
10
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