82C836 Datasheet, PDF (76/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Real Time Clock and Internal Timer Registers
Counter Operation s
GATE2
In Modes 0, 2, 3, and 4 GATE2 is level sensitive and is sampled on the rising edge of
TMRCLK. In Modes 1, 2, 3, and 5 the GATE2 input is rising-edge sensitive. This rising
edge sets an internal flip-flop whose output is sampled on the next rising edge of
TMRCLK. The flip-flop resets immediately after being sampled. Note that in Modes 2
and 3 the GATE2 input is both edge- and level-sensitive as shown in Table 6-4.
Table 6-4. Gate Pin Function
Mode
0
1
2
3
4
5
Low
Disables counting
----
a) Disables counting
b) Forces high output pin
a) Disables Counting
b) Forces high output pin
Disables counting
----
Conditions
Rising
----
a) Initiates counting
b) Resets out pin
Initiates counting
Initiates counting
----
Initiates counting
High
Enables counting
----
Enables counting
Enables counting
Enables counting
----
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 6-1 7