82C836 Datasheet, PDF (100/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Register Descriptions
DMA Controller
Figure 8-2. Command Register
B7 B6 B5 B4 B3 B2 B1 B0
________ ________ ________ ________ ________ ________ ________ ________
M-M Memory-to-Memory Transfers
AH Address Hold Feature Enable
CD Controller for DMA
CT
Compressed Timing
RP Rotating Priority Scheme
EW Extended Write
DREQ
DACK
bits: B0
B1
B2
B3
B4
B5
B6
B7
M-M
AH
CD
CT
RP
EW
DREQ
DACK
A one in the bit 0 position enables Channel 0 and Channel 1 to be
used for memory-to-memory transfers.
Writing a one to bit 1 enables the address hold feature in Channel 0
when performing memory-to-memory transfers.
Bit 2 is the master disable for the DMA controller. Writing a one to
this location disables the DMA subsystem (DMA1 or DMA2). This
function is normally used whenever the CPU needs to reprogram one
of the channels to prevent DMA cycles from occuring.
Compressed Timing is enabled by writing a one to bit 3 of this
register. The default 0 condition causes the DMA to operate with
normal timing.
Writing a one to bit 4 causes the 82C836 to utilize a rotating priority
scheme for honoring DMA requests. The default condition is fixed
priority.
Extended Write is enabled by writing a one to bit 5, causing the write
command to be asserted one DMA cycle earlier during a transfer.
The read and write commands both begin in state S2 when enabled.
DREQ active level is determined by bit 6. Writing a one in this bit
position causes DREQ to become active low.
DACK active level is determined by bit 7. Programming a one in
this bit position makes DACK an active high signal.
Mode Register
Each DMA channel has a Mode Register associated with it. All four Mode registers
reside at the same I/O address. Bits 0 and 1 of the Write Mode register command
determine which channel’s Mode register is written to. The remaining six bits control the
mode of the selected channel. Each channel’s Mode register can be read by sequentially
8-1 0 Revision 3.0
PRELIMINARY
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