82C836 Datasheet, PDF(80/205 Page) List of Unclassifed Manufacturers

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82C836 Datasheet, PDF (80/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

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s Interrupt Sequence

Interrupt Controller

Interrupt Sequence

The 82C836 allows the CPU to perform an indirect jump to a service routine in response

to a request for service from a peripheral device. The indirect jump is based on a vector

provided by the 82C836 on the second of two CPU generated INTA cycles (the first

INTA cycle is used for resolving priority; the second cycle is used for transferring the

vector to the CPU). The events occurring during an interrupt sequence are as follows:

1. One or more of the interrupt requests (IR7-IR0) becomes active, setting the

corresponding IRR bit(s).

2. The interrupt controller resolves priority based on the state of IRR, IMR, and ISR and

asserts the INTR output if appropriate.

3. The CPU accepts the interrupt and responds with an INTA cycle.

4. During the first INTA cycle, the highest priority ISR bit is set and the corresponding

IRR bit is reset. The internal Cascade address is generated and LD<0:7> outputs

remain tri-stated.

5. The CPU executes a second INTA cycle, during which the 82C836 drives an 8-bit

vector onto the data pins LD<0:7>, which is in turn latched by the CPU. The format

of this vector is shown in Table 7-2. Note that V<3:7> is programmable by writing

to Initialization Control Word 2.

6. At the end of the second INTA cycle, the ISR bit is cleared if the Automatic

End-Of-Interrupt (AEOI) mode is selected. Otherwise, the IRS bit must be cleared

by an End-Of-Interrupt (EOI) command from the CPU at the end of the interrupt

service routine.

Table 7-2. Interrupt Vector Format

Bits

Vectors

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

If no interrupt request is present at the beginning of the first INTA cycle (i.e., a spurious

interrupt), INTC1 issues an interrupt level 7 vector during the second INTA cycle.

7-4 Revision 3.0

PRELIMINARY

Chips and Technologies, Inc.

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