82C836 Datasheet, PDF (46/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Interface
DRAM Interface s
In all three modes, support is provided for 256Kx1, 256Kx4, 1Mx1, and 1Mx4 DRAMs.
In addition, MRA and SRA modes support 4MBx1 and 4MBx4 DRAMs. Corresponding
SIMM modules are also supported; including 36-bit SIMMs utilizing either dedicated
CAS signals or shared CAS between banks (the shared-CAS type cannot be used in MRA
mode).
With 4MBx1 or 4MBx4 DRAMs, a maximum of three banks can be supported. The
RAS signal for the third bank (-RAS3) becomes MA10. In non-4MB configurations, the
multiplexed memory address is limited to MA0-9.
The usage of DREQ and DACK signals in SRA and MRA modes is summarized as
follows (see Figure 5-1 shown earlier):
• In SRA mode, there are seven DREQs and seven DACKs.
• In MRA mode, two DREQs become DSEL signals to control the 74F153 multiplexer,
and three DREQs become CAS signals. Similarly, four DACKs become encoded to
drive the 74ALS138 decoder, and three DACKs become CAS signals. The net result
is six additional CAS signals as compared to SRA mode.
If parity checking is implemented, each bank is 18 bits wide: two data bytes, each of
which has one parity bit, in addition to the data bits. Parity is odd, i.e., a data byte value
of FFH will have a ‘‘one’’ for the associated parity bit. Whenever a byte or word is
written, a parity bit is generated and written along with each byte. When a read occurs,
the stored parity bit is compared to the parity calculated from the read byte. If a
mismatch occurs during a read operation, a parity error is reported and an NMI is
generated indicating a problem with memory. The NMI generation for parity errors
can be disabled using bit 6 of internal configuration register 46H, or bit 2 of I/O port
61H. If the system designer decides not to implement the parity bit (because of cost or
other reasons), NMI generation due to parity error should be disabled as described.
For minimum system parts count, the MA, RAS, CAS, MWE, and PAR signals from
the 82C836 may each drive up to 18 DRAM chips directly without buffering. This
corresponds to two SIMM modules having nine DRAM chips per module, or 6 SIMM
modules having three DRAM chips (256Kx4, 1Mx4, or 4Mx4 DRAMs) per module.
There are two SIMM modules in each memory bank. Since each CAS line drives only
one byte in each memory bank, the CAS lines effectively can drive twice as many
memory banks (in SRA or encoded RAS modes) as the MA and MWE lines. Also, since
each memory bank is driven by a separate RAS line, RAS lines do not need buffering.
The parity lines (PARL, PARH) drive only one DRAM chip in each bank and should be
able to drive up to eight banks without buffering. Similarly, the MD lines also drive only
one DRAM chip in each bank, and the 80386sx and 80387sx are both rated for high
capacitive loads. So, no buffering should be needed between MD lines and the CPU
local data bus in the typical system implementation.
A four-bank memory and architecture consisting entirely of SIMMs having three DRAM
chips each (24 DRAMs total) is a special exception to the 18-DRAM guideline. The load
distribution in this case makes MA and MWE buffering unnecessary.
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