82C836 Datasheet, PDF (62/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Real Time Clock and Internal Timer Registers
Real Time Clock Interface----MC146818 Compatible s
Table 6-2. Format for Clock, Calendar, and Alarm Data
Index Register
Address
0
1
2
3
4
5
6
7
8
9
Function
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours (12 hour mode)
Hours (24 hour mode)
Hours Alarm (12 hour mode)
Hours Alarm (24 hour mode)
Day of Week
Day of Month
Month
Year
BCD Range
00-59
00-59
00-59
00-59
01-12 (AM), 81-92 (PM)
00-23
01-12 (AM), 81-92 (PM)
00-23
01-07
01-31
01-12
00-99
Table 6-2 above shows the format for the ten clock, calendar, and alarm data. The 24/12
bit in register B determines whether the hour locations are updated using a 1-12 or 0-23
format. In 12 hour format, the high order bit of the hours byte in both the time and alarm
bytes indicates PM when it is set to one.
During uptdates, which occur once per second, the ten bytes of time, calendar, and alarm
information are unavailable to be read or written by the CPU for a period of 2ms. These
ten locations cannot be written to during this time. Information read while the Real Time
Clock is performing update is undefined. The Update Cycle section describes how
Update Cycle/PCU contention problems can be avoided.
The alarm bytes can be programmed to generate an interrupt at a specific time or they can
be programmed to generate a peroidic interrupt.
Static RAM
The 114 bytes of RAM for index address 0EH to 7FH are not affected by the Real
Time Clock. These bytes are accessible during the update cycle and may be used for
whatever the designer wishes. Typical applications use this as nonvolatile storage for
configuration and calibration parameters since this device is normally battery powered
when the system is turned off.
Chips and Technologies, Inc.
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Revision 3.0 6-3