82C836 Datasheet, PDF (37/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s System Reset and Clock Synchronization
Clock/Bus Control
• PROCCLK (processor clock) is an output clock for the 80386sx processor.
PROCCLK can be set (with internal configuration register 46H, bits 3-2) for the
following values:
° ^{PROCCLK = CXIN}
° ^{PROCCLK = CXIN/2}
° ^{PROCCLK = CXIN/4}
° ^{PROCCLK = CXIN/8}
PROCCLK can also be halted in order to implement power management techniques.
The effective speed of the 80386sx is always half the PROCCLK frequency; e.g. for an
80386sx speed of 20MHz, PROCCLK must be 40MHz. PROCCLK is derived from an
external crystal oscillator connected to CXIN.
• BUSCLK (bus clock) is an output clock for the I/O channel. BUSCLK can be set
(with internal configuration register 41H, bits 3-2) for the following values:
° ^{BUSCLK = CXIN/4}
° ^{BUSCLK = CXIN/5}
° ^{BUSCLK = CXIN/6}
The PROCCLK selection does not affect BUSCLK in either run or sleep modes.
• OSC2 (oscillator) is a 14.31818MHz output signal used by the I/O channel. The
oscillator can be derived from an external crystal connected to pins OSC1 and OSC2,
or from an external oscillator connected to OSC1 (leaving OSC2 unconnected).
• DMACLK (DMA clock) is an internal clock used by DMA controllers to time DMA
operations. DMACLK can be set (with internal configuration register 01H, bit 0) to
the following values:
° ^{DMACLK = BUSCLK}
° ^{DMACLK = BUSCLK/2 (AT-compatible)}
• SYSCLK (system clock) is an internal T-state clock used by 82C836 logic. The
frequency of SYSCLK is always PROCCLK/2.
System Reset and Clock Synchronization
SCATsx supports several different reset signals:
• PWRGOOD is the main hardware reset input to the 82C836.
• XRST is the main hardware reset output from the 82C836. It resets everything except
the CPU.
• CPURST is the CPU reset signal generated by the 82C836. It resets only the CPU.
• -RESET2 (MFP3) comes from the 8042 keyboard controller and triggers resetting of
the CPU only (CPURST).
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