82C836 Datasheet, PDF (93/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Operations s
DMA Operations
During normal operation of the 82C836, the DMA subsystem is in either an Idle
condition, a Program condition, or an Active condition. In Idle condition, the DMA
controller executes cycles consisting of only one state. The idle state, SI, is the default
condition, and the DMA remains in this condition unless the device has been initialized
and one of the DMA requests is active, or the CPU attempts to access one of the internal
registers.
When a DMA request becomes active, the device enters the Active condition and issues
a hold request to the system. Once in the Active condition, the 82C836 generates the
necessary memory addresses and command signals to accomplish a memory-to-I/O or
I/O-to-memory transfer. Timing for memory-to-memory transfer can also be generated
(but without access to the data holding register). Memory-to-I/O and I/O-to-memory
transfers take place in one bus cycle, while memory-to-memory transfer timing requires
two bus cycles. During transfers between memory and I/O, data is presented on the
system bus by either memory or the requesting device, and the transfer is completed in
one bus cycle. Memory-to-memory transfers, however, require that the DMA store data
from the read operation in an internal register, which is not accessible in AT-compatible
architectures.
During transfers between memory and I/O, two commands are activated during the same
bus cycle. In the case of a memory-to-I/O transfer, the 82C836 asserts both -XMEMR
and -IOW, allowing data to be transferred directly to the requesting device from memory.
Note, the 82C836 neither latches data from, or drives data out on this type of cycle.
The number of clock cycles required to transfer a word of data may be varied by
programming the DMA, or may be optionally extended by the peripheral device. During
an active cycle, the DMA goes through a series of states. Each state is one DMA clock
cycle in length, and the number of states in a cycle varies depending on how the device is
programmed and the type of cycle being performed. The states are labeled S0-S4.
Idle Condition
When no device is requesting service, the DMA is in an Idle condition keeping the state
machine in the SI state. During this time, the 82C836 samples the DREQ input pins
every clock cycle. The internal select from the top level decoder and HLDA are also
sampled at the same time to determine if the CPU is attempting to access the internal
registers. When either of these situations occurs, the DMA exits the idle condition.
Note, the Program condition has priority over the Active condition since a CPU cycle
has already started.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 8-3