82C836 Datasheet, PDF (53/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DRAM Interface
System Interface
Automatic Memory Configuration Detection
Typical system BIOS implementations include automatic tests to determine memory
mode and configuration without requiring user intervention. The following operational
characteristics may be useful for these BIOS algorithims:
• External hardware can be encoded RAS (SRA), nonencoded RAS (SRA), or MRA.
Encoded RAS hardware can be detected by testing Bank 0 in both encoded RAS and
nonencoded RAS (SRA) modes. Bank 0 is inaccessible in SRA mode if the external
hardware is encoded RAS, but is accessible in either SRA or MRA mode with
nonencoded RAS hardware.
• If encoded RAS hardware is detected, configuration 16H (8 banks of 1MW) can be
used to detect 256K or 1MB DRAM size. If address bit 10 is ignored, i.e., the same
physical data is accessible regardless of A10, then the DRAM is 256K. Address bit
10 corresponds to an address increment of 400H.
• With nonencoded RAS hardware, Bank 1 (if not empty) can be used to detect MRA
or SRA hardware. If the external hardware is MRA, but SRA mode is used, or vice
versa, Bank 1 is inaccessible. However, if Bank 1 is empty, there is probably no
simple way to differentiate between SRA and MRA. Schemes involving DMA
requests are possible but probably are not general enough to work in all possible
system configurations (MRA or SRA mode must still be setup correctly for the DMA
channels to operate properly).
• 256K DRAM size can be detected in Banks 0-3 using configuration code 0EH (4
banks of 1MW). If address bit 10 is ignored, i.e., same memory data accessed
regardless of A10, then the DRAM is 256K. Address bit 10 corresponds to an address
increment of 400H.
• If Bank 3 is empty and 256KW has been found in Banks 0 and 1, then Bank 2 can
be tested for 4MW using configuration 17H. Otherwise, if Banks 2 and 3 are both
empty, then Banks 0 and 1 can be tested for 4MW using configuration 19H. In either
case, address bit 11 being ignored indicates 1MB DRAM size. Address bit 11
corresponds to an address increment of 800H.
Support for External Cache
Further system performance improvement can be achieved by implementing an external
cache. Typical caches operate by ‘‘remembering ’’ a group of addresses and the data that
was last written at each address. When the same address is subsequently read back, the
cache provides the read data at a very high speed. The remembered addresses are
generally referred to as ‘‘tag’’ addresses. A ‘‘cache read hit ’’ refers to a read cycle in
which the read address matches a previously stored tag address, so the valid read data
can be provided by the cache instead of the addressed system resource. A ‘‘cache write
hit’’ refers to a write cycle in which the write address matches a stored tag address, so
the associated data for that tag address must either be updated or marked as invalid. A
‘‘cache miss’’ refers to a read or write cycle in which the read or write address does not
match any stored tag addresses. The cache can either ignore the ‘‘miss’’ cycle or
‘‘remember’’ the new tag address and associated data.
5-1 2 Revision 3.0
PRELIMINARY
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