82C836 Datasheet, PDF (96/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Transfers
DMA Controller
When programming cascaded controller, begin with the device which is actually
generating HRQ to the system (first level device) and then proceed to the second level
device. RESET causes the DACK outputs to become active low and are placed into an
inactive state. To allow the internal cascade between DMA1 and DMA2 to function
correctly, the active low state of DACK should not be modified. This is because the
82C836 has an inverter between DACK0 of DMA2 and HLDA of DMA1. This first
level device’s DMA request mask bit prevents second level cascaded devices from
generating unwanted hold requests during the initialization process.
DMA Transfers
Four types of transfer modes are provided in the 82C836 DMA subsystem. These
transfer types are:
• Read Transfer ----Read Transfers move data from memory to an I/O device by
generating the memory address and asserting -XMEMR-and -XIOW during the same
cycle.
• Write Transfer ----Write Transfers move data from an I/O device to memory by
generating the memory address and aserting -XIOR and -XMEMW.
• Memory-to-Memory Transfer ----(Not usable in AT-compatible architectures.) The
memory-to-memory transfer in an 8237 is designed to move a block of data from one
location in memory to another. DMA channels 0 and 1 may be programmed to
operate as memory-to-memory channels by setting a bit in the Command register.
Once programmed to perform a memory-to-memory transfer, the process can be
started by generating either a software request or an external request to channel 0.
Once the transfer is initiated, Channel 0 provides the address for the source block
during the memory read portion of the cycle. Channel 1 generates the address for the
memory write cycle. During the read cycle, the 8237-compatible subsection attempts
to latch a byte of data in the internal Temporary register (not accessible in
AT-compatible architectures). The 8237-compatible subsection then attempt to output
the contents of the Temporary register on the XD0-7 data lines during the write
portion of the cycle, so the data can subsequently be written to memory. However,
AT-compatible architectures, including SCATsx, do not contain the necessary data
bus steering logic to implement this data path. Channel 0 may be programmed to
maintain the same source address on every cycle, so the CPU can initialize blocks of
memory with the same value. The 82C836 continues to perform transfer cycles until
Channel 1 reaches terminal count.
• Verify Transfer ----The Verify Transfer is a pseudo-transfer useful for diagnostics. In
this type of transfer, the DMA operates as if it is performing a read or write transfer by
generating HRQ, address, and DACK, but does so without asserting a command
signal. Since no transfer actually takes place, IOCHRDY is ignored during Verify
Transfer cycles.
Auto-Initialization
Each of the four DMA channel Mode registers contain a bit that causes the channel
to reinitialize after reaching terminal count. During this process, referred to as
Auto-Initialization, the Base Address and Base Word Count registers, which were
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