EP7209 Datasheet, PDF (99/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
eXPCLK
nCS[5:0]
tnCSWR
nMWE
A[27:0]
WORD
D[31:0] _{Bus held}
EXPRDY
t8
t2
Write data
t6
t5
tADWR
t7
t2
Write data
NOTES:
1) tnCSWR = 35 nsec at 36.864 MHz
70 ns at 18.432 MHz
120 ns at 13.0 MHz
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz, and 77 nsec at 13 MHz), by either
driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed
by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when
driving EXPRDY, but is shown for clarity.
2) Consecutive reads with sequential access enabled are identical except that the sequential
access wait state field is used to determine the number of wait states, and no idle cycles are
inserted between successive non-sequential ROM/expansion cycles. This improves perfor-
mance so the SQAEN bit should always be set where possible.
3) Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin,
as this cannot be driven with valid timing under zero wait state conditions.
Figure 15. Consecutive Memory Write Cycles with Minimum Wait States
DS453PP2
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