EP7209 Datasheet, PDF (28/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
3.5.1 Interrupt Latencies in Different
States
3.5.1.1 Operating State
The ARM720T processor checks for a low level on
its FIQ and IRQ inputs at the end of each instruc-
tion. The interrupt latency is therefore directly re-
lated to the amount of time it takes to complete
execution of the current instruction when the inter-
rupt condition is detected. First, there is a one to
two clock cycle synchronization penalty. For the
case where the EP7209 is operating at 13 MHz
with a 16-bit external memory system, and instruc-
tion sequence stored in one wait state FLASH
memory, the worst case interrupt latency is
251 clock cycles. This includes a delay for cache
line fills for instruction prefetches, and a data abort
occurring at the end of the LDM instruction, and
the LDM being non-quad word aligned. In addi-
tion, the worst-case interrupt latency assumes that
LCD DMA cycles to support a panel size of 320 x
240 at 4 bits-per-pixel, 60 Hz refresh rate, is in
progress.
This would give a worst-case interrupt latency of
about 19.3 µs for the ARM720T processor operat-
ing at 13 MHz in this system. For those interrupt
inputs which have de-glitching, this figure is in-
creased by the maximum time required to pass
through the deglitcher, which is approximately 125
µs (2 cycle of the 16.384 kHz clock derived from
the RTC oscillator). This would create an absolute
worst case latency of approximately 141 µs. If the
ARM720T is run at 36 MHz or greater and/or
32 bit wide external memory, the 19.3 µs value will
be reduced.
All the serial data transfer peripherals included in
the EP7209 (except for the master-only SSI1) have
local buffering to ensure a reasonable interrupt la-
tency response requirement for the OS of 1 ms or
less. This assumes that the maximum data rates de-
scribed in this specification are complied with. If
the OS cannot meet this requirement, there will be
a risk of data over/underflow occurring. Idle State
When leaving the Idle State as a result of an inter-
rupt, the CPU clock is restarted after approximately
two clock cycles. However, there is still potentially
up to 20 µsec latency as described in the first sec-
tion above, unless the code is written to include at
least two single cycle instructions immediately af-
ter the write to the IDLE register (in which case the
latency drops to a few microseconds). This is im-
portant, as the Idle State can only be left because of
a pending interrupt, which has to be synchronized
by the processor before it can be serviced.
3.5.1.2 Standby State
In the Standby State, the latency will depend on
whether the system clock is shut down and if the
FASTWAKE bit in the SYSCON3 register is set. If
the system is configured to run from the internal
PLL clock, then the PLL will always be shut down
when in the Standby State. In this case, if the
FASTWAKE bit is cleared, then there will be a la-
tency of between 0.125 sec to 0.25 sec. If the
FASTWAKE bit is set, then there will be a latency
of between 250 µsec to 500 µsec. If the system is
running from the external clock (at 13 MHz), with
the CLKENSL bit in SYSCON2 set to 0, then the
latency will also be between 0.125 sec and 0.25 sec
to allow an external oscillator to stabilize. In the
case of a 13 MHz system where the clock is not dis-
abled during the Standby State (CLKENSL = 1),
then the latency will be the same as described in the
Idle State section above.
Whenever the EP7209 is in the Standby State, the
external address and data buses are driven low. The
RUN signal is used internally to force these buses
to be driven low. This is done to prevent peripher-
als that are power-down from draining current. Al-
so, the internal peripheral’s signals get set to their
Reset State.
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