EP7209 Datasheet, PDF (43/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
mum possible clock frequency, assuming that the
interrupt response of the target OS is sufficiently
quick.
3.11.4.3 Continuous Data Transfer
Data bytes may be sent/received in a contiguous
manner without interleaving clocks between bytes.
The frame sync control line(s) are eight clocks
apart and aligned with the clock representing bit D0
of the preceding byte (i.e., one bit in advance of the
MSB).
3.11.4.4 Discontinuous Clock
In order to save power during the idle times, the
clock line is put into a static low state. The master
is responsible for putting the link into the Idle State.
The Idle State will begin one clock, or more, after
the last byte transferred and will resume at least one
clock prior to the first frame sync assertion. To dis-
able the clock, the TX section is turned off.
In Master mode, the EP7209 does not support the
discontinuous clock.
3.11.4.5 Error Conditions
RX FIFO overflows are detected and conveyed via
a status bit in the SYSFLG2 register. This register
should be accessed at periodic intervals by the ap-
plication software. The status register should be
read each time the RX FIFO interrupts are generat-
ed. At this time the error condition (i.e., overrun
flag) will indicate that an error has occurred but
cannot convey which byte contains the error. Writ-
ing to the SRXEOF register location clears the
overrun flag. TX FIFO underflow condition is de-
tected and conveyed via a bit in the SYSFLG2 reg-
ister, which is accessed by the application software.
A TX underflow error is cleared by writing data to
be transmitted to the TX FIFO.
3.11.4.6 Clock Polarity
Clock polarity is fixed. TX data is presented on the
bus on the rising edge of the clock. Data is latched
into the receiving device on the falling edge of the
clock. The TX pin is held in a tristate condition
when not transmitting.
3.12 LCD Controller with Support for On-
Chip Frame Buffer
The LCD controller provides all the necessary con-
trol signals to interface directly to a single panel
multiplexed LCD. The panel size is programmable
and can be any width (line length) from 32 to
1024 pixels in 16 pixel increments. The total video
frame buffer size is programmable up to 128
kbytes. This equates to a theoretical maximum pan-
el size of 1024 x 256 pixels in 4-bits-per-pixel
mode. The video frame buffer can be located in any
portion of memory controlled by the chip selects.
Its start address will be fixed at address 0x0000000
within each chip select. The start address of the
LCD video frame buffer is defined in the FBAD-
DR[3:0] register. These bits become the most sig-
nificant nibble of the external address bus. The
default start address is 0xC000 0000 (FBADDR =
0xC). A system built using the on-chip SRAM
(OCSR), will then serve as the LCD video frame
buffer and miscellaneous data store. The LCD vid-
eo frame buffer start address should be set to 0x6 in
this option. Programming of the register FBADDR
is only permitted when the LCD is disabled (this is
to avoid possible cycle corruption when changing
the register contents while a LCD DMA cycle is in
progress). There is no hardware protection to pre-
vent this. It is necessary for the software to disable
the LCD controller before reprogramming the
FBADDR register. Full address decoding is pro-
vided for the OCSR, up to the maximum video
frame buffer size programmable into the LCDCON
register. Beyond this, the address is wrapped
around. The frame buffer start address must not be
programmed to 0x4 or 0x5 if either CL-PS6700 in-
DS453PP2
43