EP7209 Datasheet, PDF (9/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
Table 14. Boot Options ................................................................................................................. 30
Table 15. CL-PS6700 Memory Map.............................................................................................. 31
Table 16. Space Field Decoding ................................................................................................... 32
Table 19. Serial Interface Options................................................................................................. 35
Table 20. Serial-Pin Assignments ................................................................................................. 35
Table 21. ADC Interface Operation Frequencies .......................................................................... 39
Table 17. Effect of Endianness on Read Operations .................................................................... 41
Table 18. Effect of Endianness on Write Operations .................................................................... 41
Table 22. Instructions Supported in JTAG Mode .......................................................................... 47
Table 23. Device ID Register ........................................................................................................ 48
Table 24. EP7209 Memory Map in External Boot Mode ............................................................... 50
Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)............. 52
Table 26. EP7209 Internal Registers (Big Endian Mode) ............................................................. 54
Table 27. SYSCON1 ..................................................................................................................... 56
Table 28. SYSCON2 ..................................................................................................................... 59
Table 29. SYSCON3 ..................................................................................................................... 61
Table 30. SYSFLG ........................................................................................................................ 62
Table 31. SYSFLG2 ...................................................................................................................... 64
Table 32. INTSR1 ......................................................................................................................... 65
Table 34. INTSR3 ......................................................................................................................... 68
Table 35. Values of the Bus Width Field ....................................................................................... 70
Table 36. Values of the Wait State Field at 13 MHz and 18 MHz ................................................. 70
Table 37. Values of the Wait State Field at 36 MHz ..................................................................... 70
Table 38. MEMCFG ...................................................................................................................... 71
Table 39. LED Flash Rates ........................................................................................................... 72
Table 40. LED Duty Ratio ............................................................................................................. 72
Table 41. PMPCON ...................................................................................................................... 73
Table 42. Sense of PWM control lines .......................................................................................... 73
Table 43. UARTDR1-2 UART1-2 .................................................................................................. 74
Table 44. UBRLCR1-2 UART1-2 .................................................................................................. 75
Table 45. LCDCON ....................................................................................................................... 77
Table 46. Gray Scale Value to Color Mapping.............................................................................. 79
Table 47. SYNCIO ........................................................................................................................ 80
Table 48. DAI Control Register ..................................................................................................... 84
Table 49. DAI Data Register 0 ...................................................................................................... 87
Table 50. DAI Data Register 1 ...................................................................................................... 88
Table 51. DAI Control, Data and Status Register Locations ......................................................... 91
Table 52. absolute Maximum Ratings........................................................................................... 93
Table 53. Recommended Operating Conditions ........................................................................... 93
Table 54. DC Characteristics ........................................................................................................ 93
Table 55. AC Timing Characteristics............................................................................................. 95
Table 56. Timing Characteristics................................................................................................... 96
Table 57. I/O Buffer Output Characteristics ................................................................................ 102
Table 58. 208-Pin LQFP Numeric Pin Listing ............................................................................. 102
Table 59. EP7209 Hardware Test Modes ................................................................................... 106
Table 60. Oscillator and PLL Test Mode Signals ........................................................................ 107
Table 61. Software Selectable Test Functionality ....................................................................... 107
Table 62. 208-Pin LQFP Numeric Pin Listing ............................................................................. 109
Table 63. 256-Ball PBGA Ball Listing.......................................................................................... 113
Table 64. PBGA Balls to Connect to Ground (V_SS) .................................................................... 116
DS453PP2
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