EP7209 Datasheet, PDF (46/128 Pages) Cirrus Logic – Ultra-Low-Power Audio Decoder System-on-Chip

EP7209
(thus generating a 500 kHz frequency when using
the 13 MHz source). This divider is enabled by set-
ting the OSTB (Operating System Timing Bit) in
the SYSCON2 register (bit 12). When this bit is set
high to select the 500 kHz mode, the 500 kHz fre-
quency is routed to the timers instead of the
541 kHz clock. This does not affect the frequencies
derived for any of the other internal peripherals.
The timer counters can operate in two modes: free
running or pre-scale.
3.13.1 Free Running Mode
In the free running mode, the counter will wrap
around to 0xFFFF when it under flows and it will
continue to count down. Any value written to TC1
or TC2 will be decremented on the second edge of
the selected clock.
3.13.2 Prescale Mode
In the prescale mode, the value written to TC1 or
TC2 is automatically re-loaded when the counter
under flows. Any value written to TC1 or TC2 will
be decremented on the second edge of the selected
clock. This mode can be used to produce a pro-
grammable frequency to drive the buzzer (i.e., with
TC1) or generate a periodic interrupt.
3.14 Real Time Clock
The EP7209 contains a 32-bit Real Time Clock
(RTC). This can be written to and read from in the
same way as the timer counters, but it is 32 bits
wide. The RTC is always clocked at 1 Hz, generat-
ed from the 32.768 kHz oscillator. It also contains
a 32-bit output match register, this can be pro-
grammed to generate an interrupt when the time in
the RTC matches a specific time written to this reg-
ister. The RTC can only be reset by an nPOR cold
reset. Because the RTC data register is updated
from the 1 Hz clock derived from the 32 kHz
source, which is asynchronous to the main memory
system clock, the data register should always be
read twice to ensure a valid and stable reading. This
also applies when reading back the RTCDIV field
of the SYSCON1 register, which reflects the status
of the six LSBs of the RTC counter.
3.14.1 Characteristics of the Real Time
Clock Interface
When connecting a crystal to the RTC interface
pins (i.e., RTCIN and RTCOUT), the crystal and
circuit should conform to the following require-
ments:
• The 32.768 kHz frequency should be created
by the crystals fundamental tone (i.e., it should
be a fundamental mode crystal)
• A start-up resistor is not necessary, since one is
provided internally.
• Start-up loading capacitors may be placed on
each side of the external crystal and ground.
Their value should be in the range of 10 pF.
However, their values should be selected based
upon the crystal specifications. The total sum of
the capacitance of the traces between the
EP7209’s clock pins, the capacitors, and the
crystal leads should be subtracted from the
crystal’s specifications when determining the
values for the loading capacitors.
• The crystal should have a maximum 5 ppm fre-
quency drift over the chip’s operating tempera-
ture range.
• The voltage for the crystal must be 2.5 V + 0.2 V.
Alternatively, a digital clock source can be used to
drive the RTCIN pin of the EP7209. With this ap-
proach, the voltage levels of the clock source
should match that of the Vdd supply for the
EP7209’s pads (i.e., the supply voltage level used
to drive all of the non-Vdd core pins on the
EP7209) (i.e., RTCOUT). The output clock pin
should be left floating.
46
DS453PP2